[PATCH] D141189: [Mips] Set setMaxAtomicSizeInBitsSupported

[YunQiang Su via Phabricator via llvm-commits]

wzssyqa added inline comments.


================
Comment at: llvm/lib/Target/Mips/MipsISelLowering.cpp:500-501
+    setMaxAtomicSizeInBitsSupported(32);
+  else
+    setMaxAtomicSizeInBitsSupported(0);
+
----------------
brad wrote:
> wzssyqa wrote:
> > brad wrote:
> > > arsenm wrote:
> > > > Else case doesn't make sense to me but I know nothing about mips 
> > > > Else case doesn't make sense to me but I know nothing about mips 
> > > 
> > > To deal with MIPS-I not having support for atomics.
> > Sorry for me. I am no idea about what's the mean of the value of `setMaxAtomicSizeInBitsSupported`.
> > 
> > Maybe:
> > 1) load/store instructions no quirky behavior: an instruction can be split to in result.
> >     If so, MIPS has never this problem since MIPS I.
> > 2) normal load/store instructions can make sure that the data sync in a multicore system.
> >     If so, MIPS never archives this.
> > 3) architecture has some instructions to help atomic ops.
> >     If so, MIPS has LL/SC since MIPS II.
> setMaxAtomicSizeInBitsSupported() indicates the maximum size of supported atomic operations that are *all* lock-free. 32-bit MIPS does not have hardware support for lock-free 64-bit atomics.
Ohh, Yes, ldc1 is available since MIPS II.

and 

```
ldc1 $f0, 0($4)
mfc1 $2, $f0
mfc1 $3, $f1
```
is wrong for MIPS32 FP64 ABI.
For MIPS32 FP64 ABI(support MIPS32R2+ only), it should be like:
```
ldc1 $f0, 0($4)
mfc1 $2, $f0
mfhc1 $3, $f0
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141189/new/

https://reviews.llvm.org/D141189