[PATCH] D142071: [RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added a comment.

In D142071#4099927 <https://reviews.llvm.org/D142071#4099927>, @reames wrote:

> Based on your prior comment, I think your regression here comes down to how we lower uadd_with_overflow.  It looks like our lowering of that could use some improvement.
>
> You could investigate improving that and then returning here.  Another option to consider is where we should be returning false from TLI->shouldFormOverflowOp.  (Either case, the result should be a separate patch and this one should then depend on it.)

Thanks.

A deeper look at the ARM's lowering. 
RISCV may need `setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);`

Reference @rogfer01’s D35192 <https://reviews.llvm.org/D35192>

Testcase:

  declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
  define i64 @optbranch_64(i64 %Arg) {
  bb:
    %0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %Arg, i64 -1)
    %math = extractvalue { i64, i1 } %0, 0
    %ov = extractvalue { i64, i1 } %0, 1
    %.math = select i1 %ov, i64 -1, i64 %math
    ret i64 %.math
  }

Step 2: Optimized lowered selection DAG: %bb.0, Arm and RISCV are the same.

  SelectionDAG has 18 nodes:
    t0: ch,glue = EntryToken
        t2: i32,ch = CopyFromReg t0, Register:i32 %0
        t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t5: i64 = build_pair t2, t4
    t7: i64,i1 = uaddo t5, Constant:i64<-1>
    t8: i64 = select t7:1, Constant:i64<-1>, t7
      t12: i32 = extract_element t8, Constant:i32<0>
    t14: ch,glue = CopyToReg t0, Register:i32 $r0, t12
      t10: i32 = extract_element t8, Constant:i32<1>
    t16: ch,glue = CopyToReg t14, Register:i32 $r1, t10, t14:1
    t17: ch = ARMISD::RET_FLAG t16, Register:i32 $r0, Register:i32 $r1, t16:1

but step 3, 
ARM: Type-legalized selection DAG:

  Type-legalized selection DAG: %bb.0 'optbranch_64:bb'
  SelectionDAG has 18 nodes:
    t0: ch,glue = EntryToken
      t23: i32 = select t28, Constant:i32<-1>, t21
    t14: ch,glue = CopyToReg t0, Register:i32 $r0, t23
      t24: i32 = select t28, Constant:i32<-1>, t22
    t16: ch,glue = CopyToReg t14, Register:i32 $r1, t24, t14:1
      t2: i32,ch = CopyFromReg t0, Register:i32 %0
    t21: i32,i32 = uaddo t2, Constant:i32<-1>
      t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t26: i32 = and t21:1, Constant:i32<1>
    t22: i32,i32 = addcarry t4, Constant:i32<-1>, t26
    t28: i32 = and t22:1, Constant:i32<1>
    t17: ch = ARMISD::RET_FLAG t16, Register:i32 $r0, Register:i32 $r1, t16:1

RISCV: 
Type-legalized selection DAG: %bb.0 'optbranch_64:bb'

  SelectionDAG has 24 nodes:
    t0: ch,glue = EntryToken
    t2: i32,ch = CopyFromReg t0, Register:i32 %0
    t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t31: i32 = select t38, Constant:i32<-1>, t26
    t14: ch,glue = CopyToReg t0, Register:i32 $x10, t31
      t32: i32 = select t38, Constant:i32<-1>, t29
    t16: ch,glue = CopyToReg t14, Register:i32 $x11, t32, t14:1
    t26: i32 = add t2, Constant:i32<-1>
    t28: i32 = setcc t26, t2, setult:ch
      t27: i32 = add t4, Constant:i32<-1>
    t29: i32 = add t27, t28
        t35: i32 = setcc t29, t4, seteq:ch
        t33: i32 = setcc t29, t4, setult:ch
      t36: i32 = select t35, t28, t33
    t38: i32 = and t36, Constant:i32<1>
    t17: ch = RISCVISD::RET_FLAG t16, Register:i32 $x10, Register:i32 $x11, t16:1

ARM seems to have introduced new nodes `ARMISD::ADDC` and `ARMISD::ADDE`
I need more time to implement this feature because I haven't sorted out the logic yet.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D142071