[PATCH] D142461: [SPARC] Lower BR_CC to BPr on 64-bit target whenever possible
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 2 18:29:12 PST 2023
arsenm added inline comments.
================
Comment at: llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp:45
case Sparc::fixup_sparc_br16_2:
- return (Value >> 2) & 0xc000;
+ return ((Value >> 2) & 0xc000) << 6;
----------------
koakuma wrote:
> Not really sure if this is the proper way to do it, but I've found that without the left shift, the integrated assembler would misplace the two upper bits of BPr branch displacements.
> Comments?
I know nothing about this, but it seems like it should be split into a separate patch
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142461/new/
https://reviews.llvm.org/D142461
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