[PATCH] D143036: [RISCV] Add vendor-defined XTHeadBs (single-bit) extension

Thu Feb 2 08:29:40 PST 2023

philipp.tomsich added a comment.

In D143036#4099959 <https://reviews.llvm.org/D143036#4099959>, @craig.topper wrote:

> Any plan to support `RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial`, `RISCVTargetLowering::hasBitTest`, `performTRUNCATECombine` or `performANDCombine`?

Yes, this is planned in a follow-up optimization ... if that is ok?
The plan is to get the basic support (such as in these initial patches) in and then add more optimizations as we run SPEC against the full set of extensions.

For XTHeadBb (which is the next one from the series that will go to Phabricator), there is some DAGToDAG work to support bit-extract instructions (i.e. similar to how AArch64 handles the formation of UBFM and SBFM nodes).
This will also be split off into a separate patch.

Ok to defer? Or would you rather have this go in with the initial enablement?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143036/new/

https://reviews.llvm.org/D143036