[PATCH] D143154: [AMDGPU] Introduce divergence and uniform bit fields in tablegen

[Yashwant Singh via Phabricator via llvm-commits]

yassingh created this revision.
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IsSourceOfDivergence and IsAlwaysUniform can be set to 1 to mark instructions
which are inherently divergent or uniform. Adding them to Readlane and 
Writelane instruction for now. To be extended to all required instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143154

Files:
  llvm/lib/Target/AMDGPU/SIDefines.h
  llvm/lib/Target/AMDGPU/SIInstrFormats.td
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/always-uniform.mir
  llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/never-uniform.mir

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