[PATCH] D142997: [RISCV] Move the even register check for rv32zdinx later in the matching process.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:377-379
+  bool isGPRF64AsFPR() const { return isGPR() && Reg.IsGPRAsFPR; }
 
+  bool isGPRPF64AsFPR() const { return isGPR() && Reg.IsGPRAsFPR; }
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jrtc27 wrote:
> Is there a reason we'd want to keep these two and not just use isGPRAsFPR everywhere?
No. I'm going to do another pass through this as a follow up. My focus was on getting rid of IsRV64 on register operands.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142997/new/

https://reviews.llvm.org/D142997