[PATCH] D143029: [RISCV] Add vendor-defined XTHeadBa (address-generation) extension

[Philipp Tomsich via Phabricator via llvm-commits]

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The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba.  It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1 <https://reviews.llvm.org/D1>) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBa is
available from:

  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:

  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143029

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv64xtheadba.ll
  llvm/test/MC/RISCV/rv64xtheadba-invalid.s
  llvm/test/MC/RISCV/rv64xtheadba-valid.s

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