[llvm] 6ab4d6e - [RISCV][NFC] Update RISCVUsage.rst to sort vendor extensions

[Philipp Tomsich via llvm-commits]

Author: Philipp Tomsich
Date: 2023-02-01T01:13:52+01:00
New Revision: 6ab4d6e44eb0bda03a57f43fbf3c88b9901210b9

URL: https://github.com/llvm/llvm-project/commit/6ab4d6e44eb0bda03a57f43fbf3c88b9901210b9
DIFF: https://github.com/llvm/llvm-project/commit/6ab4d6e44eb0bda03a57f43fbf3c88b9901210b9.diff

LOG: [RISCV][NFC] Update RISCVUsage.rst to sort vendor extensions

Added: 
    

Modified: 
    llvm/docs/RISCVUsage.rst

Removed: 
    


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diff  --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 58a24cea30885..3b6b7b54916a0 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -169,12 +169,11 @@ It is our intention to follow the naming conventions described in `riscv-non-isa
 
 The current vendor extensions supported are:
 
-``XVentanaCondOps``
-  LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
-
 ``XTHeadVdot``
   LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
+``XVentanaCondOps``
+  LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 Specification Documents
 =======================