[llvm] d255e0f - [RISCV] Peak through BITCAST in isUsedByReturnOnly

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-01-30T23:41:14Z
New Revision: d255e0f99716cdd18c60f3e8ea4ef8c7f57fe3a3

URL: https://github.com/llvm/llvm-project/commit/d255e0f99716cdd18c60f3e8ea4ef8c7f57fe3a3
DIFF: https://github.com/llvm/llvm-project/commit/d255e0f99716cdd18c60f3e8ea4ef8c7f57fe3a3.diff

LOG: [RISCV] Peak through BITCAST in isUsedByReturnOnly

A follow up to 47b1f8362aa409b591b5e9c8a9ff0e3e1d76ed9c,
This covers some more cases on soft-float ABIs with the f/d extension.
I left the TODO in as there is still the case where we need to handle rv32i without f/d, but that looks like it requires changes to SelectionDAGLegalize::ExpandFPLibCall

Reviewed By: asb, reames

Differential Revision: https://reviews.llvm.org/D142911

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/float-frem.ll
    llvm/test/CodeGen/RISCV/libcall-tail-calls.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4223ab98de842..296a5090045b4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13263,6 +13263,11 @@ bool RISCVTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
     return false;
 
   SDNode *Copy = *N->use_begin();
+  
+  if (Copy->getOpcode() == ISD::BITCAST) {
+    return isUsedByReturnOnly(Copy, Chain);
+  }
+  
   // TODO: Handle additional opcodes in order to support tail-calling libcalls
   // with soft float ABIs.
   if (Copy->getOpcode() != ISD::CopyToReg) {

diff  --git a/llvm/test/CodeGen/RISCV/float-frem.ll b/llvm/test/CodeGen/RISCV/float-frem.ll
index ce63cb48c9fc0..d8e90b2029e6c 100644
--- a/llvm/test/CodeGen/RISCV/float-frem.ll
+++ b/llvm/test/CodeGen/RISCV/float-frem.ll
@@ -11,12 +11,7 @@
 define float @frem_f32(float %a, float %b) nounwind {
 ; RV32IF-LABEL: frem_f32:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    addi sp, sp, -16
-; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    call fmodf at plt
-; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    addi sp, sp, 16
-; RV32IF-NEXT:    ret
+; RV32IF-NEXT:    tail fmodf at plt
 ;
 ; RV64IF-LABEL: frem_f32:
 ; RV64IF:       # %bb.0:

diff  --git a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
index c6fa51f8571aa..9389a4b5bc8a5 100644
--- a/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
+++ b/llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
@@ -240,14 +240,18 @@ define float @sin_f32(float %a) nounwind {
 ; F-ABI-ALL:       # %bb.0:
 ; F-ABI-ALL-NEXT:    tail sinf at plt
 ;
-; RV32-ILP32-ALL-LABEL: sin_f32:
-; RV32-ILP32-ALL:       # %bb.0:
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, -16
-; RV32-ILP32-ALL-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32-ALL-NEXT:    call sinf at plt
-; RV32-ILP32-ALL-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, 16
-; RV32-ILP32-ALL-NEXT:    ret
+; RV32IFD-ILP32-LABEL: sin_f32:
+; RV32IFD-ILP32:       # %bb.0:
+; RV32IFD-ILP32-NEXT:    tail sinf at plt
+;
+; RV32I-ILP32-LABEL: sin_f32:
+; RV32I-ILP32:       # %bb.0:
+; RV32I-ILP32-NEXT:    addi sp, sp, -16
+; RV32I-ILP32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32-NEXT:    call sinf at plt
+; RV32I-ILP32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32-NEXT:    addi sp, sp, 16
+; RV32I-ILP32-NEXT:    ret
 ;
 ; RV64-LP64-ALL-LABEL: sin_f32:
 ; RV64-LP64-ALL:       # %bb.0:
@@ -272,14 +276,18 @@ define float @powi_f32(float %a, i32 %b) nounwind {
 ; RV32IF-ILP32F:       # %bb.0:
 ; RV32IF-ILP32F-NEXT:    tail __powisf2 at plt
 ;
-; RV32-ILP32-ALL-LABEL: powi_f32:
-; RV32-ILP32-ALL:       # %bb.0:
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, -16
-; RV32-ILP32-ALL-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32-ALL-NEXT:    call __powisf2 at plt
-; RV32-ILP32-ALL-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-ILP32-ALL-NEXT:    addi sp, sp, 16
-; RV32-ILP32-ALL-NEXT:    ret
+; RV32IFD-ILP32-LABEL: powi_f32:
+; RV32IFD-ILP32:       # %bb.0:
+; RV32IFD-ILP32-NEXT:    tail __powisf2 at plt
+;
+; RV32I-ILP32-LABEL: powi_f32:
+; RV32I-ILP32:       # %bb.0:
+; RV32I-ILP32-NEXT:    addi sp, sp, -16
+; RV32I-ILP32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32-NEXT:    call __powisf2 at plt
+; RV32I-ILP32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32-NEXT:    addi sp, sp, 16
+; RV32I-ILP32-NEXT:    ret
 ;
 ; RV64IFD-LP64D-LABEL: powi_f32:
 ; RV64IFD-LP64D:       # %bb.0:
@@ -390,14 +398,18 @@ define double @sin_f64(double %a) nounwind {
 ; RV64IF-LP64F-NEXT:    addi sp, sp, 16
 ; RV64IF-LP64F-NEXT:    ret
 ;
-; RV64-LP64-ALL-LABEL: sin_f64:
-; RV64-LP64-ALL:       # %bb.0:
-; RV64-LP64-ALL-NEXT:    addi sp, sp, -16
-; RV64-LP64-ALL-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-LP64-ALL-NEXT:    call sin at plt
-; RV64-LP64-ALL-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-LP64-ALL-NEXT:    addi sp, sp, 16
-; RV64-LP64-ALL-NEXT:    ret
+; RV64IFD-LP64-LABEL: sin_f64:
+; RV64IFD-LP64:       # %bb.0:
+; RV64IFD-LP64-NEXT:    tail sin at plt
+;
+; RV64I-LP64-LABEL: sin_f64:
+; RV64I-LP64:       # %bb.0:
+; RV64I-LP64-NEXT:    addi sp, sp, -16
+; RV64I-LP64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64-NEXT:    call sin at plt
+; RV64I-LP64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64-NEXT:    addi sp, sp, 16
+; RV64I-LP64-NEXT:    ret
   %1 = call double @llvm.sin.f64(double %a)
   ret double %1
 }