[PATCH] D141842: [LoopVectorize] Enable integer Mul and Add as select reduction patterns

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 492687.
MattDevereau added a comment.

This patch landed a few days ago but was reverted due to a miscompile.

I've added the tests `non_reduction_index` and `non_reduction_index_half` which are reproducers for the miscompile. One of the operands of the binary op in a select of a binary op against a phi node must be the false select operand in order to be reduced. This error caused a miscompile of what should be an index decrement to be a vectorized reduction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141842/new/

https://reviews.llvm.org/D141842

Files:
  llvm/lib/Analysis/IVDescriptors.cpp
  llvm/test/Transforms/LoopVectorize/if-reduction.ll

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