[PATCH] D142612: [RISCV][NFC] Add test for register coalescing x0

[Luke Lau via Phabricator via llvm-commits]

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Ideally all the `COPY $x0`s would be coalesced here, but register
allocator doesn't seem to like the fact that %1 lives across multiple
basic blocks
Part of https://github.com/llvm/llvm-project/issues/56872


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142612

Files:
  llvm/test/CodeGen/RISCV/regcoal-constreg.mir


Index: llvm/test/CodeGen/RISCV/regcoal-constreg.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/regcoal-constreg.mir
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32-- -run-pass=simple-register-coalescing %s | FileCheck %s
+--- |
+  define void @func() { ret void }
+...
+---
+name: func
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+body: |
+  ; CHECK-LABEL: name: func
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x0
+  ; CHECK-NEXT:   BNE $x0, [[COPY]], %bb.2
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   dead [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY1]], 1
+  bb.0:
+    %0 = COPY $x0
+    %1 = COPY $x0
+    BNE %0, %1, %bb.2
+    PseudoBR %bb.1
+
+  bb.1:
+    %1 = COPY $x0
+
+  bb.2:
+    %2 = ADDI %1, 1
+
+...


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