[PATCH] D141853: [ARM] Accept shortened forms of the T2 ADC instruction

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 25 05:51:17 PST 2023


dmgreen added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:1026
 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
-                             bit Commutable = 0> {
+                             bit Commutable = 0, bit PostISelHook = 0> {
+  let Defs = [CPSR], Uses = [CPSR], hasPostISelHook = PostISelHook in {
----------------
lenary wrote:
> dmgreen wrote:
> > Nit: It looks like PostISelHook needn't be a parameter if it is always passed 1. 
> I wasn't sure if other instructions wanted to use `T2I_adde_sube_irs` without `PostISelHook`, even though none do right now, which is why i suggested this approach, but maybe the instruction definitions are now stable enough that this would be fine?
It's not a big deal either way. Arm is fairly stable though, and if the parameter is needed by another patch I would suggest it should be simple enough to add there.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141853/new/

https://reviews.llvm.org/D141853



More information about the llvm-commits mailing list