[PATCH] D141853: [ARM] Accept shortened forms of the T2 ADC instruction
Sam Elliott via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 25 05:43:53 PST 2023
lenary added inline comments.
================
Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:1026
multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
- bit Commutable = 0> {
+ bit Commutable = 0, bit PostISelHook = 0> {
+ let Defs = [CPSR], Uses = [CPSR], hasPostISelHook = PostISelHook in {
----------------
dmgreen wrote:
> Nit: It looks like PostISelHook needn't be a parameter if it is always passed 1.
I wasn't sure if other instructions wanted to use `T2I_adde_sube_irs` without `PostISelHook`, even though none do right now, which is why i suggested this approach, but maybe the instruction definitions are now stable enough that this would be fine?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D141853/new/
https://reviews.llvm.org/D141853
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