[PATCH] D142516: [SVE] Move isel for casting between NEON and SVE vector types into tablegen.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4017
 
-// NOTE: We cannot use EXTRACT_SUBREG in all cases because the fixed length
-// vector types larger than NEON don't have a matching SubRegIndex.
-static SDNode *extractSubReg(SelectionDAG *DAG, EVT VT, SDValue V) {
-  assert(V.getValueType().isScalableVector() &&
-         V.getValueType().getSizeInBits().getKnownMinValue() ==
-             AArch64::SVEBitsPerBlock &&
-         "Expected to extract from a packed scalable vector!");
-  assert(VT.isFixedLengthVector() &&
-         "Expected to extract a fixed length vector!");
+bool AArch64DAGToDAGISel::trySelectCastFixedLengthToScalableVector(SDNode *N) {
+  assert(N->getOpcode() == ISD::INSERT_SUBVECTOR && "Invalid Node!");
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To aid reviewing please note the diff has been made worse because the new functions are in the opposite order when compared to the original code, because I've maintained alphabetical ordering.  The mapping is:
extractSubReg -> trySelectCastScalableToFixedLengthVector
insertSubReg -> trySelectCastFixedLengthToScalableVector




Repository:
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  https://reviews.llvm.org/D142516/new/

https://reviews.llvm.org/D142516