[PATCH] D142264: [RISCV] Combine extract_vector_elt followed by VFMV_S_F_VL.

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10577
+        return Src.getOperand(0);
+      // TODO: Use insert_subvector/extract_subvector to change widen/narrow?
+    }
----------------
Do we need to handle the case when VL=0 and the destination register is preserved?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142264/new/

https://reviews.llvm.org/D142264