[PATCH] D142144: [RISCV][Driver] Add -rvv-vector-bits= option similar to -sve-vector-bits=

[Fangrui Song via Phabricator via llvm-commits]

MaskRay added inline comments.


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Comment at: clang/docs/ReleaseNotes.rst:844
   take architecture extensions from ``-march`` if both are given.
+- Added -rvv-vector-bits= option to give an upper bound on vector length. Valid
+  values are powers of 2 between 64 and 65536. We also accept "zvl" to use
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Comment at: clang/include/clang/Driver/Options.td:3588
+           " vector length agnostic value of \"scalable\". Also accepts \"zvl\""
+           " to use the value implied by -march/-mcpu. (RISC-V only)">;
 
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Conform to the majority style, not the few exceptions


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Comment at: clang/test/Driver/riscv-rvv-vector-bits.c:5
+
+// RUN: %clang -c %s -### -target riscv64-linux-gnu -march=rv64gc_zve64x \
+// RUN:  -mrvv-vector-bits=128 2>&1 | FileCheck --check-prefix=CHECK-128 %s
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`--target=`

`-target ` is legacy.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D142144/new/

https://reviews.llvm.org/D142144