[llvm] 08a19d7 - [AArch64][SME2] MOVA tile-to-vector and vector-to-tile should not accept VG suffix
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 23 05:11:15 PST 2023
Author: Sander de Smalen
Date: 2023-01-23T13:10:09Z
New Revision: 08a19d76171ecb20821bd808efe84381a0581f3c
URL: https://github.com/llvm/llvm-project/commit/08a19d76171ecb20821bd808efe84381a0581f3c
DIFF: https://github.com/llvm/llvm-project/commit/08a19d76171ecb20821bd808efe84381a0581f3c.diff
LOG: [AArch64][SME2] MOVA tile-to-vector and vector-to-tile should not accept VG suffix
Reviewed By: MattDevereau
Differential Revision: https://reviews.llvm.org/D141601
Added:
Modified:
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/test/MC/AArch64/SME2/mova-diagnostics.s
llvm/test/MC/AArch64/SME2p1/movaz-diagnostics.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index f8c97ca00394a..8378fb64eb8b3 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -2995,7 +2995,7 @@ class sme2_mova_vec_to_tile_vg2_multi_base<bits<2> sz, bit v,
string mnemonic>
: I<(outs tile_ty:$ZAd),
(ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm, vector_ty:$Zn),
- mnemonic, "\t$ZAd[$Rs, $imm, vgx2], $Zn",
+ mnemonic, "\t$ZAd[$Rs, $imm], $Zn",
"", []>, Sched<[]> {
bits<2> Rs;
bits<4> Zn;
@@ -3156,7 +3156,7 @@ class sme2_mova_vec_to_tile_vg4_multi_base<bits<2> sz, bit v, bits<3> op,
(ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm,
vector_ty:$Zn),
mnemonic,
- "\t$ZAd[$Rs, $imm, vgx4], $Zn",
+ "\t$ZAd[$Rs, $imm], $Zn",
"", []>, Sched<[]> {
bits<2> Rs;
bits<3> Zn;
@@ -3477,7 +3477,7 @@ class sme2_mova_tile_to_vec_vg2_multi_base<bits<2> sz, bit v, bits<3> op,
: I<!if(op{1}, (outs vector_ty:$Zd, tile_ty:$_ZAn), (outs vector_ty:$Zd)),
(ins tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm),
mnemonic,
- "\t$Zd, $ZAn[$Rs, $imm, vgx2]",
+ "\t$Zd, $ZAn[$Rs, $imm]",
"", []>, Sched<[]> {
bits<4> Zd;
bits<2> Rs;
@@ -3618,7 +3618,7 @@ class sme2_mova_tile_to_vec_vg4_multi_base<bits<2> sz, bit v, bits<6> op,
: I<!if(op{4}, (outs vector_ty:$Zd, tile_ty:$_ZAn), (outs vector_ty:$Zd)),
(ins tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm),
mnemonic,
- "\t$Zd, $ZAn[$Rs, $imm, vgx4]",
+ "\t$Zd, $ZAn[$Rs, $imm]",
"", []>, Sched<[]> {
bits<3> Zd;
bits<2> Rs;
diff --git a/llvm/test/MC/AArch64/SME2/mova-diagnostics.s b/llvm/test/MC/AArch64/SME2/mova-diagnostics.s
index 2839e2f9e26e6..71ac7042a6b7e 100644
--- a/llvm/test/MC/AArch64/SME2/mova-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/mova-diagnostics.s
@@ -71,3 +71,47 @@ mov {z0.h-z3.h}, za.d[w8, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h
// CHECK-NEXT: mov {z0.h-z3.h}, za.d[w8, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Tile-to-vector and vector-to-tile should not accept the VG suffix
+
+mov za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2p1/movaz-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/movaz-diagnostics.s
index 276dd907a9eb9..2b6bc03d7f3bb 100644
--- a/llvm/test/MC/AArch64/SME2p1/movaz-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/movaz-diagnostics.s
@@ -98,3 +98,16 @@ movaz z31.s, za1h.d[w15, -1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
// CHECK-NEXT: movaz z31.s, za1h.d[w15, -1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Tile-to-vector should not accept the VG suffix
+
+movaz { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movaz { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movaz { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movaz { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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