[llvm] 2faebde - [AArch64][SME2] NFC: Simplify multiclasses for mova/movaz.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 23 05:11:14 PST 2023
Author: Sander de Smalen
Date: 2023-01-23T13:10:09Z
New Revision: 2faebdef97cef7020569144a5767947c044b53c4
URL: https://github.com/llvm/llvm-project/commit/2faebdef97cef7020569144a5767947c044b53c4
DIFF: https://github.com/llvm/llvm-project/commit/2faebdef97cef7020569144a5767947c044b53c4.diff
LOG: [AArch64][SME2] NFC: Simplify multiclasses for mova/movaz.
Reviewed By: CarolineConcatto
Differential Revision: https://reviews.llvm.org/D142198
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 308ca07d4461..42a44c62363b 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -616,8 +616,8 @@ defm MOVA_4ZMXI : sme2_mova_tile_to_vec_vg4_multi<"mova">;
defm MOVA_VG2_MXI2Z : sme2_mova_vec_to_array_vg2_multi<"mova">;
defm MOVA_VG4_MXI4Z : sme2_mova_vec_to_array_vg4_multi<"mova">;
-defm MOVA_VG2_2ZMXI : sme2_mova_array_to_vec_vg2_multi<"mova">;
-defm MOVA_VG4_4ZMXI : sme2_mova_array_to_vec_vg4_multi<"mova">;
+defm MOVA_VG2_2ZMXI : sme2_mova_array_to_vec_vg2_multi<0b000, "mova">;
+defm MOVA_VG4_4ZMXI : sme2_mova_array_to_vec_vg4_multi<0b1000, "mova">;
defm SQRSHR_VG2_Z2ZI : sme2_sat_shift_vector_vg2<"sqrshr", 0b0, 0b0>;
defm SQRSHR_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshr", 0b000>;
@@ -802,8 +802,8 @@ let Predicates = [HasSME2p1] in {
defm MOVAZ_ZMI : sme2p1_movaz_tile_to_vec<"movaz">;
defm MOVAZ_2ZMI : sme2p1_movaz_tile_to_vec_vg2<"movaz">;
defm MOVAZ_4ZMI : sme2p1_movaz_tile_to_vec_vg4<"movaz">;
-defm MOVAZ_VG2_2ZM : sme2p1_movaz_array_to_vec_vg2<"movaz">;
-defm MOVAZ_VG4_4ZM : sme2p1_movaz_array_to_vec_vg4<"movaz">;
+defm MOVAZ_VG2_2ZM : sme2_mova_array_to_vec_vg2_multi<0b010, "movaz">;
+defm MOVAZ_VG4_4ZM : sme2_mova_array_to_vec_vg4_multi<0b1100, "movaz">;
defm ZERO_MXI : sme2p1_zero_matrix<"zero">;
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index cc05c7ca9427..f8c97ca00394 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -3506,10 +3506,9 @@ def : InstAlias<mnemonic # "\t$Zd, $ZAn[$Rs, $imm" # !if(!eq(vg_acronym, ""), ""
}
-// SME2 move tile to vector, two registers
-multiclass sme2_mova_tile_to_vec_vg2_multi_inst<bit v, string mnemonic> {
+multiclass sme2_mova_tile_to_vec_vg2_multi_inst<bit v, bits<3> opc, string mnemonic> {
- def _B : sme2_mova_tile_to_vec_vg2_multi_base<0b00, v, 0b000, ZZ_b_mul_r,
+ def _B : sme2_mova_tile_to_vec_vg2_multi_base<0b00, v, opc, ZZ_b_mul_r,
!if(v, TileVectorOpV8,
TileVectorOpH8),
uimm3s2range, mnemonic> {
@@ -3517,7 +3516,7 @@ multiclass sme2_mova_tile_to_vec_vg2_multi_inst<bit v, string mnemonic> {
let Inst{7-5} = imm;
}
- def _H : sme2_mova_tile_to_vec_vg2_multi_base<0b01, v, 0b000, ZZ_h_mul_r,
+ def _H : sme2_mova_tile_to_vec_vg2_multi_base<0b01, v, opc, ZZ_h_mul_r,
!if(v, TileVectorOpV16,
TileVectorOpH16),
uimm2s2range, mnemonic> {
@@ -3527,7 +3526,7 @@ multiclass sme2_mova_tile_to_vec_vg2_multi_inst<bit v, string mnemonic> {
let Inst{6-5} = imm;
}
- def _S : sme2_mova_tile_to_vec_vg2_multi_base<0b10, v, 0b000, ZZ_s_mul_r,
+ def _S : sme2_mova_tile_to_vec_vg2_multi_base<0b10, v, opc, ZZ_s_mul_r,
!if(v, TileVectorOpV32,
TileVectorOpH32),
uimm1s2range, mnemonic> {
@@ -3537,7 +3536,7 @@ multiclass sme2_mova_tile_to_vec_vg2_multi_inst<bit v, string mnemonic> {
let Inst{5} = imm;
}
- def _D : sme2_mova_tile_to_vec_vg2_multi_base<0b11, v, 0b000, ZZ_d_mul_r,
+ def _D : sme2_mova_tile_to_vec_vg2_multi_base<0b11, v, opc, ZZ_d_mul_r,
!if(v, TileVectorOpV64,
TileVectorOpH64),
uimm0s2range, mnemonic> {
@@ -3545,6 +3544,7 @@ multiclass sme2_mova_tile_to_vec_vg2_multi_inst<bit v, string mnemonic> {
let Inst{7-5} = ZAn;
}
+ if !eq(mnemonic, "mova") then {
defm : sme2_mova_tile_or_array_to_vec_aliases<1,!cast<Instruction>(NAME # _B),
ZZ_b_mul_r,
!if(v, TileVectorOpV8,
@@ -3569,103 +3569,47 @@ multiclass sme2_mova_tile_to_vec_vg2_multi_inst<bit v, string mnemonic> {
TileVectorOpH64),
MatrixIndexGPR32Op12_15,
uimm0s2range, "mov">;
+ }
defm : sme2_mova_tile_or_array_to_vec_aliases<0,!cast<Instruction>(NAME # _B),
ZZ_b_mul_r,
!if(v, TileVectorOpV8,
TileVectorOpH8),
MatrixIndexGPR32Op12_15,
- uimm3s2range, "mova">;
+ uimm3s2range, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0,!cast<Instruction>(NAME # _H),
ZZ_h_mul_r,
!if(v, TileVectorOpV16,
TileVectorOpH16),
MatrixIndexGPR32Op12_15,
- uimm2s2range, "mova">;
+ uimm2s2range, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _S),
ZZ_s_mul_r,
!if(v, TileVectorOpV32,
TileVectorOpH32),
MatrixIndexGPR32Op12_15,
- uimm1s2range, "mova">;
+ uimm1s2range, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _D),
ZZ_d_mul_r,
!if(v, TileVectorOpV64,
TileVectorOpH64),
MatrixIndexGPR32Op12_15,
- uimm0s2range, "mova">;
+ uimm0s2range, mnemonic>;
}
+// SME2 move tile to vector, two registers
multiclass sme2_mova_tile_to_vec_vg2_multi<string mnemonic>{
- defm _H : sme2_mova_tile_to_vec_vg2_multi_inst<0b0, mnemonic>;
- defm _V : sme2_mova_tile_to_vec_vg2_multi_inst<0b1, mnemonic>;
-}
-
-// SME2.1 zeroing move tile to vector, two registers
-multiclass sme2p1_movaz_tile_to_vec_vg2_base<bit v, string mnemonic> {
- def _B : sme2_mova_tile_to_vec_vg2_multi_base<0b00, v, 0b010, ZZ_b_mul_r,
- !if(v, TileVectorOpV8, TileVectorOpH8),
- uimm3s2range, mnemonic> {
- bits<3> imm;
- let Inst{7-5} = imm;
- }
-
- def _H : sme2_mova_tile_to_vec_vg2_multi_base<0b01, v, 0b010, ZZ_h_mul_r,
- !if(v, TileVectorOpV16, TileVectorOpH16),
- uimm2s2range, mnemonic> {
- bits<1> ZAn;
- bits<2> imm;
- let Inst{7} = ZAn;
- let Inst{6-5} = imm;
- }
-
- def _S : sme2_mova_tile_to_vec_vg2_multi_base<0b10, v, 0b010, ZZ_s_mul_r,
- !if(v, TileVectorOpV32, TileVectorOpH32),
- uimm1s2range, mnemonic> {
- bits<2> ZAn;
- bits<1> imm;
- let Inst{7-6} = ZAn;
- let Inst{5} = imm;
- }
-
- def _D : sme2_mova_tile_to_vec_vg2_multi_base<0b11, v, 0b010, ZZ_d_mul_r,
- !if(v, TileVectorOpV64, TileVectorOpH64),
- uimm0s2range, mnemonic> {
- bits<3> ZAn;
- let Inst{7-5} = ZAn;
- }
-
- defm : sme2_mova_tile_or_array_to_vec_aliases<0,!cast<Instruction>(NAME # _B),
- ZZ_b_mul_r,
- !if(v, TileVectorOpV8,
- TileVectorOpH8),
- MatrixIndexGPR32Op12_15,
- uimm3s2range, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0,!cast<Instruction>(NAME # _H),
- ZZ_h_mul_r,
- !if(v, TileVectorOpV16,
- TileVectorOpH16),
- MatrixIndexGPR32Op12_15,
- uimm2s2range, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _S),
- ZZ_s_mul_r,
- !if(v, TileVectorOpV32,
- TileVectorOpH32),
- MatrixIndexGPR32Op12_15,
- uimm1s2range, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _D),
- ZZ_d_mul_r,
- !if(v, TileVectorOpV64,
- TileVectorOpH64),
- MatrixIndexGPR32Op12_15,
- uimm0s2range, "movaz">;
+ defm _H : sme2_mova_tile_to_vec_vg2_multi_inst<0b0, 0b000, mnemonic>;
+ defm _V : sme2_mova_tile_to_vec_vg2_multi_inst<0b1, 0b000, mnemonic>;
}
+// SME2p1 move tile to vector and zero tile, two registers
multiclass sme2p1_movaz_tile_to_vec_vg2<string mnemonic>{
- defm _H : sme2p1_movaz_tile_to_vec_vg2_base<0b0, mnemonic>;
- defm _V : sme2p1_movaz_tile_to_vec_vg2_base<0b1, mnemonic>;
+ defm _H : sme2_mova_tile_to_vec_vg2_multi_inst<0b0, 0b010, mnemonic>;
+ defm _V : sme2_mova_tile_to_vec_vg2_multi_inst<0b1, 0b010, mnemonic>;
}
+
class sme2_mova_tile_to_vec_vg4_multi_base<bits<2> sz, bit v, bits<6> op,
RegisterOperand vector_ty,
RegisterOperand tile_ty,
@@ -3691,10 +3635,9 @@ class sme2_mova_tile_to_vec_vg4_multi_base<bits<2> sz, bit v, bits<6> op,
let Constraints = !if(op{4}, "$ZAn = $_ZAn", "");
}
-// SME2 move tile to vector, four registers
-multiclass sme2_mova_tile_to_vec_vg4_multi_base<bit v, string mnemonic> {
+multiclass sme2_mova_tile_to_vec_vg4_multi_base<bit v, bits<3> opc, string mnemonic> {
- def _B : sme2_mova_tile_to_vec_vg4_multi_base<0b00, v, {0b1000,?,?},
+ def _B : sme2_mova_tile_to_vec_vg4_multi_base<0b00, v, {opc,0,?,?},
ZZZZ_b_mul_r,
!if(v, TileVectorOpV8,
TileVectorOpH8),
@@ -3703,7 +3646,7 @@ multiclass sme2_mova_tile_to_vec_vg4_multi_base<bit v, string mnemonic> {
let Inst{6-5} = imm;
}
- def _H : sme2_mova_tile_to_vec_vg4_multi_base<0b01, v, {0b1000,?,?},
+ def _H : sme2_mova_tile_to_vec_vg4_multi_base<0b01, v, {opc,0,?,?},
ZZZZ_h_mul_r,
!if(v, TileVectorOpV16,
TileVectorOpH16),
@@ -3714,7 +3657,7 @@ multiclass sme2_mova_tile_to_vec_vg4_multi_base<bit v, string mnemonic> {
let Inst{5} = imm;
}
- def _S : sme2_mova_tile_to_vec_vg4_multi_base<0b10, v, {0b1000,?,?},
+ def _S : sme2_mova_tile_to_vec_vg4_multi_base<0b10, v, {opc,0,?,?},
ZZZZ_s_mul_r,
!if(v, TileVectorOpV32,
TileVectorOpH32),
@@ -3723,7 +3666,7 @@ multiclass sme2_mova_tile_to_vec_vg4_multi_base<bit v, string mnemonic> {
let Inst{6-5} = ZAn;
}
- def _D : sme2_mova_tile_to_vec_vg4_multi_base<0b11, v, {0b100,?,?,?},
+ def _D : sme2_mova_tile_to_vec_vg4_multi_base<0b11, v, {opc,?,?,?},
ZZZZ_d_mul_r,
!if(v, TileVectorOpV64,
TileVectorOpH64),
@@ -3732,6 +3675,7 @@ multiclass sme2_mova_tile_to_vec_vg4_multi_base<bit v, string mnemonic> {
let Inst{7-5} = ZAn;
}
+ if !eq(mnemonic, "mova") then {
defm : sme2_mova_tile_or_array_to_vec_aliases<1, !cast<Instruction>(NAME # _B),
ZZZZ_b_mul_r,
!if(v, TileVectorOpV8,
@@ -3756,99 +3700,45 @@ multiclass sme2_mova_tile_to_vec_vg4_multi_base<bit v, string mnemonic> {
TileVectorOpH64),
MatrixIndexGPR32Op12_15,
uimm0s4range, "mov">;
+ }
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _B),
ZZZZ_b_mul_r,
!if(v, TileVectorOpV8,
TileVectorOpH8),
MatrixIndexGPR32Op12_15,
- uimm2s4range, "mova">;
+ uimm2s4range, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _H),
ZZZZ_h_mul_r,
!if(v, TileVectorOpV16,
TileVectorOpH16),
MatrixIndexGPR32Op12_15,
- uimm1s4range, "mova">;
+ uimm1s4range, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _S),
ZZZZ_s_mul_r,
!if(v, TileVectorOpV32,
TileVectorOpH32),
MatrixIndexGPR32Op12_15,
- uimm0s4range, "mova">;
+ uimm0s4range, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _D),
ZZZZ_d_mul_r,
!if(v, TileVectorOpV64,
TileVectorOpH64),
MatrixIndexGPR32Op12_15,
- uimm0s4range, "mova">;
+ uimm0s4range, mnemonic>;
}
-multiclass sme2_mova_tile_to_vec_vg4_multi<string mnemonic>{
- defm _H : sme2_mova_tile_to_vec_vg4_multi_base<0b0, mnemonic>;
- defm _V : sme2_mova_tile_to_vec_vg4_multi_base<0b1, mnemonic>;
-}
-
-// SME2.1 zeroing move tile to vector, four registers
-multiclass sme2p1_movaz_tile_to_vec_vg4_base<bit v, string mnemonic> {
- def _B : sme2_mova_tile_to_vec_vg4_multi_base<0b00, v, {0b1100,?,?}, ZZZZ_b_mul_r,
- !if(v, TileVectorOpV8, TileVectorOpH8),
- uimm2s4range, mnemonic> {
- bits<2> imm;
- let Inst{6-5} = imm;
- }
- def _H : sme2_mova_tile_to_vec_vg4_multi_base<0b01, v, {0b1100,?,?}, ZZZZ_h_mul_r,
- !if(v, TileVectorOpV16, TileVectorOpH16),
- uimm1s4range, mnemonic> {
- bits<1> ZAn;
- bits<1> imm;
- let Inst{6} = ZAn;
- let Inst{5} = imm;
- }
-
- def _S : sme2_mova_tile_to_vec_vg4_multi_base<0b10, v, {0b1100,?,?}, ZZZZ_s_mul_r,
- !if(v, TileVectorOpV32, TileVectorOpH32),
- uimm0s4range, mnemonic> {
- bits<2> ZAn;
- let Inst{6-5} = ZAn;
- }
-
- def _D : sme2_mova_tile_to_vec_vg4_multi_base<0b11, v, {0b110,?,?,?}, ZZZZ_d_mul_r,
- !if(v, TileVectorOpV64, TileVectorOpH64),
- uimm0s4range, mnemonic> {
- bits<3> ZAn;
- let Inst{7-5} = ZAn;
- }
-
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _B),
- ZZZZ_b_mul_r,
- !if(v, TileVectorOpV8,
- TileVectorOpH8),
- MatrixIndexGPR32Op12_15,
- uimm2s4range, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _H),
- ZZZZ_h_mul_r,
- !if(v, TileVectorOpV16,
- TileVectorOpH16),
- MatrixIndexGPR32Op12_15,
- uimm1s4range, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _S),
- ZZZZ_s_mul_r,
- !if(v, TileVectorOpV32,
- TileVectorOpH32),
- MatrixIndexGPR32Op12_15,
- uimm0s4range, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME # _D),
- ZZZZ_d_mul_r,
- !if(v, TileVectorOpV64,
- TileVectorOpH64),
- MatrixIndexGPR32Op12_15,
- uimm0s4range, "movaz">;
+// SME2 move tile to vector, four registers
+multiclass sme2_mova_tile_to_vec_vg4_multi<string mnemonic>{
+ defm _H : sme2_mova_tile_to_vec_vg4_multi_base<0b0, 0b100, mnemonic>;
+ defm _V : sme2_mova_tile_to_vec_vg4_multi_base<0b1, 0b100, mnemonic>;
}
+// SME2p1 move tile to vector and zero tile, four registers
multiclass sme2p1_movaz_tile_to_vec_vg4<string mnemonic>{
- defm _H : sme2p1_movaz_tile_to_vec_vg4_base<0b0, mnemonic>;
- defm _V : sme2p1_movaz_tile_to_vec_vg4_base<0b1, mnemonic>;
+ defm _H : sme2_mova_tile_to_vec_vg4_multi_base<0b0, 0b110, mnemonic>;
+ defm _V : sme2_mova_tile_to_vec_vg4_multi_base<0b1, 0b110, mnemonic>;
}
@@ -3872,50 +3762,45 @@ class sme2_mova_array_to_vec_vg24_multi<bits<4>op, RegisterOperand vector_ty,
let Constraints = !if(op{2}, "$ZAn = $_ZAn", "");
}
-class sme2_mova_array_to_vec_vg2_multi<bits<4> op, RegisterOperand vector_ty,
- RegisterOperand array_ty,
- string mnemonic>
- : sme2_mova_array_to_vec_vg24_multi<op, vector_ty, array_ty, mnemonic,
- "vgx2"> {
- bits<4> Zd;
- let Inst{4-1} = Zd;
-}
-
-// MOVA (array to vector, two registers)
-multiclass sme2_mova_array_to_vec_vg2_multi<string mnemonic> {
- def NAME : sme2_mova_array_to_vec_vg2_multi<{0b000,?}, ZZ_d_mul_r, MatrixOp64,
- mnemonic>;
+// move array to vector, two registers.
+multiclass sme2_mova_array_to_vec_vg2_multi<bits<3> opc, string mnemonic> {
+ def NAME : sme2_mova_array_to_vec_vg24_multi<{opc,?}, ZZ_d_mul_r, MatrixOp64,
+ mnemonic, "vgx2"> {
+ bits<4> Zd;
+ let Inst{4-1} = Zd;
+ }
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_b_mul_r, MatrixOp8,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_h_mul_r, MatrixOp16,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_s_mul_r, MatrixOp32,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_d_mul_r, MatrixOp64,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_b_mul_r, MatrixOp8,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova", "vgx2">;
+ sme_elm_idx0_7, mnemonic, "vgx2">;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_h_mul_r, MatrixOp16,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova", "vgx2">;
+ sme_elm_idx0_7, mnemonic, "vgx2">;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_s_mul_r, MatrixOp32,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova", "vgx2">;
+ sme_elm_idx0_7, mnemonic, "vgx2">;
+ if !eq(mnemonic, "mova") then {
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZ_b_mul_r, MatrixOp8,
MatrixIndexGPR32Op8_11,
@@ -3949,88 +3834,48 @@ multiclass sme2_mova_array_to_vec_vg2_multi<string mnemonic> {
ZZ_d_mul_r, MatrixOp64,
MatrixIndexGPR32Op8_11,
sme_elm_idx0_7, "mov", "vgx2">;
+ }
}
-// SME2.1 MOVAZ (array to vector, two registers)
-multiclass sme2p1_movaz_array_to_vec_vg2<string mnemonic> {
- def NAME : sme2_mova_array_to_vec_vg2_multi<{0b010,?}, ZZ_d_mul_r, MatrixOp64,
- mnemonic>;
-
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZ_b_mul_r, MatrixOp8,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZ_h_mul_r, MatrixOp16,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZ_s_mul_r, MatrixOp32,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZ_d_mul_r, MatrixOp64,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
-
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZ_b_mul_r, MatrixOp8,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz", "vgx2">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZ_h_mul_r, MatrixOp16,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz", "vgx2">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZ_s_mul_r, MatrixOp32,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz", "vgx2">;
-}
-
-class sme2_mova_array_to_vec_vg4_multi<bits<4> op, RegisterOperand vector_ty,
- RegisterOperand array_ty,
- string mnemonic>
- : sme2_mova_array_to_vec_vg24_multi<op, vector_ty, array_ty, mnemonic,
- "vgx4"> {
- bits<3> Zd;
- let Inst{4-2} = Zd;
-}
-
-// MOVA (array to vector, four registers)
-multiclass sme2_mova_array_to_vec_vg4_multi<string mnemonic> {
- def NAME : sme2_mova_array_to_vec_vg4_multi<0b1000, ZZZZ_d_mul_r, MatrixOp64,
- mnemonic>;
+// move array to vector, four registers
+multiclass sme2_mova_array_to_vec_vg4_multi<bits<4> opc, string mnemonic> {
+ def NAME : sme2_mova_array_to_vec_vg24_multi<opc, ZZZZ_d_mul_r, MatrixOp64,
+ mnemonic, "vgx4"> {
+ bits<3> Zd;
+ let Inst{4-2} = Zd;
+ }
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_b_mul_r, MatrixOp8,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_h_mul_r, MatrixOp16,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_s_mul_r, MatrixOp32,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_d_mul_r, MatrixOp64,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova">;
+ sme_elm_idx0_7, mnemonic>;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_b_mul_r, MatrixOp8,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova", "vgx4">;
+ sme_elm_idx0_7, mnemonic, "vgx4">;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_h_mul_r, MatrixOp16,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova", "vgx4">;
+ sme_elm_idx0_7, mnemonic, "vgx4">;
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_s_mul_r, MatrixOp32,
MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "mova", "vgx4">;
+ sme_elm_idx0_7, mnemonic, "vgx4">;
+ if !eq(mnemonic, "mova") then {
defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_b_mul_r, MatrixOp8,
MatrixIndexGPR32Op8_11,
@@ -4064,42 +3909,7 @@ multiclass sme2_mova_array_to_vec_vg4_multi<string mnemonic> {
ZZZZ_d_mul_r, MatrixOp64,
MatrixIndexGPR32Op8_11,
sme_elm_idx0_7, "mov", "vgx4">;
-}
-
-// SME2.1 MOVAZ (array to vector, four registers)
-multiclass sme2p1_movaz_array_to_vec_vg4<string mnemonic> {
- def NAME : sme2_mova_array_to_vec_vg4_multi<0b1100, ZZZZ_d_mul_r, MatrixOp64,
- mnemonic>;
-
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZZZ_b_mul_r, MatrixOp8,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZZZ_h_mul_r, MatrixOp16,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZZZ_s_mul_r, MatrixOp32,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZZZ_d_mul_r, MatrixOp64,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz">;
-
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZZZ_b_mul_r, MatrixOp8,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz", "vgx4">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZZZ_h_mul_r, MatrixOp16,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz", "vgx4">;
- defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
- ZZZZ_s_mul_r, MatrixOp32,
- MatrixIndexGPR32Op8_11,
- sme_elm_idx0_7, "movaz", "vgx4">;
+ }
}
//===----------------------------------------------------------------------===//
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