[PATCH] D142079: [TableGen] Support custom decoders for variable length instructions

[Min-Yih Hsu via Phabricator via llvm-commits]

myhsu added a comment.

In D142079#4071791 <https://reviews.llvm.org/D142079#4071791>, @RKSimon wrote:

> In D142079#4071770 <https://reviews.llvm.org/D142079#4071770>, @Paul-C-Anagnostopoulos wrote:
>
>> The TableGen Programmer's Reference does not include descriptions of backend facilities.
>
> So maybe BackGuide.rst ?

I don't think it will be a good place since it's for TableGen backend developers while this patch only adds new TG directives for disassembler developers. Right now, IMO, the most related document is actually Writing an LLVM Backend <https://llvm.org/docs/WritingAnLLVMBackend.html>, which is the only place mentioning TG syntax for writing instruction encodings (for fixed-length instructions, of course). Instead of cluttering with Writing an LLVM Backend I feel like a better way will be creating a separate page for variable-length instruction encoding / decoding.


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