[llvm] 0ee04a1 - ARM: Add baseline test for fneg + fcmp + select combine
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 22 17:21:21 PST 2023
Author: Matt Arsenault
Date: 2023-01-22T21:21:15-04:00
New Revision: 0ee04a1e3cba0f544e718fe252a7b964b7335615
URL: https://github.com/llvm/llvm-project/commit/0ee04a1e3cba0f544e718fe252a7b964b7335615
DIFF: https://github.com/llvm/llvm-project/commit/0ee04a1e3cba0f544e718fe252a7b964b7335615.diff
LOG: ARM: Add baseline test for fneg + fcmp + select combine
Added:
llvm/test/CodeGen/ARM/unsafe-fneg-select-minnum-maxnum-combine.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/unsafe-fneg-select-minnum-maxnum-combine.ll b/llvm/test/CodeGen/ARM/unsafe-fneg-select-minnum-maxnum-combine.ll
new file mode 100644
index 000000000000..d18295fc0132
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/unsafe-fneg-select-minnum-maxnum-combine.ll
@@ -0,0 +1,227 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=arm-- -mattr=+fullfp16 < %s | FileCheck %s
+
+define float @select_fneg_a_or_8_cmp_olt_a_neg8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_fneg_a_or_8_cmp_olt_a_neg8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #-8.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s4, #8.000000e+00
+; CHECK-NEXT: vneg.f32 s6, s2
+; CHECK-NEXT: vcmp.f32 s0, s2
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s6, s4
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %fneg.a = fneg nnan nsz float %a
+ %cmp.a = fcmp nnan nsz olt float %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
+ ret float %min.a
+}
+
+define half @select_fneg_a_or_8_cmp_olt_a_neg8_f16(half %a, half %b) #0 {
+; CHECK-LABEL: select_fneg_a_or_8_cmp_olt_a_neg8_f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vmov.f16 s0, #-8.000000e+00
+; CHECK-NEXT: vcmp.f16 s0, s4
+; CHECK-NEXT: vmov.f16 s2, #8.000000e+00
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vneg.f16 s6, s4
+; CHECK-NEXT: vselgt.f16 s0, s6, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %fneg.a = fneg nnan nsz half %a
+ %cmp.a = fcmp nnan nsz olt half %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, half %fneg.a, half 8.0
+ ret half %min.a
+}
+
+define float @select_fneg_a_or_8_cmp_ogt_a_neg8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_fneg_a_or_8_cmp_ogt_a_neg8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #-8.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s4, #8.000000e+00
+; CHECK-NEXT: vneg.f32 s6, s2
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s6, s4
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %fneg.a = fneg nnan nsz float %a
+ %cmp.a = fcmp nnan nsz ogt float %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0
+ ret float %min.a
+}
+
+define half @select_fneg_a_or_8_cmp_ogt_a_neg8_f16(half %a, half %b) #0 {
+; CHECK-LABEL: select_fneg_a_or_8_cmp_ogt_a_neg8_f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vmov.f16 s0, #-8.000000e+00
+; CHECK-NEXT: vcmp.f16 s4, s0
+; CHECK-NEXT: vmov.f16 s2, #8.000000e+00
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vneg.f16 s6, s4
+; CHECK-NEXT: vselgt.f16 s0, s6, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %fneg.a = fneg nnan nsz half %a
+ %cmp.a = fcmp nnan nsz ogt half %a, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, half %fneg.a, half 8.0
+ ret half %min.a
+}
+
+define float @select_fsub0_or_8_cmp_olt_fsub1_neg8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_fsub0_or_8_cmp_olt_fsub1_neg8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #4.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s4, #-8.000000e+00
+; CHECK-NEXT: vmov.f32 s8, #8.000000e+00
+; CHECK-NEXT: vsub.f32 s6, s0, s2
+; CHECK-NEXT: vsub.f32 s0, s2, s0
+; CHECK-NEXT: vcmp.f32 s4, s6
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s0, s8
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %sub.0 = fsub nnan nsz float 4.0, %a
+ %sub.1 = fsub nnan nsz float %a, 4.0
+ %cmp.a = fcmp nnan nsz olt float %sub.0, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %sub.1, float 8.0
+ ret float %min.a
+}
+
+define float @select_fsub0_or_neg8_cmp_olt_fsub1_8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_fsub0_or_neg8_cmp_olt_fsub1_8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #4.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s4, #8.000000e+00
+; CHECK-NEXT: vmov.f32 s8, #-8.000000e+00
+; CHECK-NEXT: vsub.f32 s6, s0, s2
+; CHECK-NEXT: vsub.f32 s0, s2, s0
+; CHECK-NEXT: vcmp.f32 s4, s6
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s0, s8
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %sub.0 = fsub nnan nsz float 4.0, %a
+ %sub.1 = fsub nnan nsz float %a, 4.0
+ %cmp.a = fcmp nnan nsz olt float %sub.0, 8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %sub.1, float -8.0
+ ret float %min.a
+}
+
+define float @select_mul4_or_neg8_cmp_olt_mulneg4_8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_mul4_or_neg8_cmp_olt_mulneg4_8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s6, #8.000000e+00
+; CHECK-NEXT: vmov.f32 s4, #4.000000e+00
+; CHECK-NEXT: vmov.f32 s8, #-8.000000e+00
+; CHECK-NEXT: vmul.f32 s0, s2, s0
+; CHECK-NEXT: vmul.f32 s2, s2, s4
+; CHECK-NEXT: vcmp.f32 s6, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s8
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %mul.0 = fmul nnan nsz float %a, 4.0
+ %mul.1 = fmul nnan nsz float %a, -4.0
+ %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0
+ ret float %min.a
+}
+
+define float @select_mul4_or_8_cmp_olt_mulneg4_neg8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_mul4_or_8_cmp_olt_mulneg4_neg8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s6, #-8.000000e+00
+; CHECK-NEXT: vmov.f32 s4, #4.000000e+00
+; CHECK-NEXT: vmov.f32 s8, #8.000000e+00
+; CHECK-NEXT: vmul.f32 s0, s2, s0
+; CHECK-NEXT: vmul.f32 s2, s2, s4
+; CHECK-NEXT: vcmp.f32 s6, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s8
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %mul.0 = fmul nnan nsz float %a, 4.0
+ %mul.1 = fmul nnan nsz float %a, -4.0
+ %cmp.a = fcmp nnan nsz olt float %mul.1, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float 8.0
+ ret float %min.a
+}
+
+define float @select_mul4_or_8_cmp_olt_mulneg4_8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_mul4_or_8_cmp_olt_mulneg4_8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s6, #8.000000e+00
+; CHECK-NEXT: vmov.f32 s4, #4.000000e+00
+; CHECK-NEXT: vmul.f32 s0, s2, s0
+; CHECK-NEXT: vmul.f32 s2, s2, s4
+; CHECK-NEXT: vcmp.f32 s6, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s6
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %mul.0 = fmul nnan nsz float %a, 4.0
+ %mul.1 = fmul nnan nsz float %a, -4.0
+ %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float 8.0
+ ret float %min.a
+}
+
+define float @select_mul4_or_neg8_cmp_olt_mulneg4_neg8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_mul4_or_neg8_cmp_olt_mulneg4_neg8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #-4.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s6, #-8.000000e+00
+; CHECK-NEXT: vmov.f32 s4, #4.000000e+00
+; CHECK-NEXT: vmul.f32 s0, s2, s0
+; CHECK-NEXT: vmul.f32 s2, s2, s4
+; CHECK-NEXT: vcmp.f32 s6, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s6
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %mul.0 = fmul nnan nsz float %a, 4.0
+ %mul.1 = fmul nnan nsz float %a, -4.0
+ %cmp.a = fcmp nnan nsz olt float %mul.1, -8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0
+ ret float %min.a
+}
+
+define float @select_mulneg4_or_neg8_cmp_olt_mul4_8_f32(float %a, float %b) #0 {
+; CHECK-LABEL: select_mulneg4_or_neg8_cmp_olt_mul4_8_f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #4.000000e+00
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.f32 s6, #8.000000e+00
+; CHECK-NEXT: vmov.f32 s4, #-4.000000e+00
+; CHECK-NEXT: vmov.f32 s8, #-8.000000e+00
+; CHECK-NEXT: vmul.f32 s0, s2, s0
+; CHECK-NEXT: vmul.f32 s2, s2, s4
+; CHECK-NEXT: vcmp.f32 s6, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s8
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mov pc, lr
+ %mul.0 = fmul nnan nsz float %a, -4.0
+ %mul.1 = fmul nnan nsz float %a, 4.0
+ %cmp.a = fcmp nnan nsz olt float %mul.1, 8.0
+ %min.a = select nnan nsz i1 %cmp.a, float %mul.0, float -8.0
+ ret float %min.a
+}
+
+; FIXME: Should be unnecessary
+attributes #0 = { "no-signed-zeros-fp-math"="true" }
More information about the llvm-commits
mailing list