[PATCH] D142071: [RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy updated this revision to Diff 491212.
liaolucy added a comment.

1. grabbing the optbranch_32 test case from SystemZ
2. add CHECK lines for RV32

3. optbranch_64 with RV32 has regression，thanks Alex. I don't have a solution for the regression now. Any suggestions？

I analyze ARM and SystemZ:

RISCV: after codegenprepare, generate @llvm.uadd.with.overflow.i64 + extractvalue，which causes the regression

- IR Dump After CodeGen Prepare (codegenprepare) ***

define i64 @optbranch_64(i64 %Arg) {
bb:

  %0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %Arg, i64 1)
  %math = extractvalue { i64, i1 } %0, 0
  %ov = extractvalue { i64, i1 } %0, 1
  br i1 %ov, label %bb2, label %bb3

bb2:                                              ; preds = %bb

  ret i64 -1

bb3:                                              ; preds = %bb

  ret i64 %math

}

ARM has simplifycfg pass before codegenprepare:

- IR Dump After Simplify the CFG (simplifycfg) ***

define i64 @optbranch_64(i64 %Arg) {
bb:

  %i1 = icmp eq i64 %Arg, -1
  %i4 = add nuw i64 %Arg, 1
  %common.ret.op = select i1 %i1, i64 -1, i64 %i4
  ret i64 %common.ret.op

}

systemZ is the same as RISCV, generate @llvm.uadd.with.overflow.i64 + extractvalue, but SystemZ seems to have the register pairs $r2d.

- IR Dump After SystemZ DAG->DAG Pattern Instruction Selection (systemz-isel) ***: Machine code for function optbranch_64: IsSSA, TracksLiveness

Function Live Ins: $r2d in %1

bb.0.bb:

  successors: %bb.1(0x40000000), %bb.2(0x40000000); %bb.1(50.00%), %bb.2(50.00%)
  liveins: $r2d
  %1:gr64bit = COPY $r2d
  %0:gr64bit = ALGHSIK %1:gr64bit, 1, implicit-def $cc
  BRC 15, 12, %bb.2, implicit $cc
  J %bb.1

bb.1.bb2:
; predecessors: %bb.0

  %2:gr64bit = LGHI -1
  $r2d = COPY %2:gr64bit
  Return implicit $r2d

bb.2.bb3:
; predecessors: %bb.0

  $r2d = COPY %0:gr64bit
  Return implicit $r2d


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142071/new/

https://reviews.llvm.org/D142071

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/branch-on-zero.ll

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