[llvm] 2e8aa2d - [PowerPC] Regenerate vec_absd.ll test checks
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 22 09:20:07 PST 2023
Author: Simon Pilgrim
Date: 2023-01-22T17:19:48Z
New Revision: 2e8aa2dcbcd8f825fc0b6e8677ca009d990dbf1e
URL: https://github.com/llvm/llvm-project/commit/2e8aa2dcbcd8f825fc0b6e8677ca009d990dbf1e
DIFF: https://github.com/llvm/llvm-project/commit/2e8aa2dcbcd8f825fc0b6e8677ca009d990dbf1e.diff
LOG: [PowerPC] Regenerate vec_absd.ll test checks
Added:
Modified:
llvm/test/CodeGen/PowerPC/vec_absd.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/vec_absd.ll b/llvm/test/CodeGen/PowerPC/vec_absd.ll
index 1ae3ee5d2590a..e554cca1ddcaf 100644
--- a/llvm/test/CodeGen/PowerPC/vec_absd.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_absd.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
@@ -13,33 +14,40 @@ declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)
declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>)
define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_byte:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vabsdub 2, 2, 3
+; CHECK-NEXT: blr
entry:
%res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
-; CHECK-LABEL: @test_byte
-; CHECK: vabsdub 2, 2, 3
-; CHECK: blr
}
define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_half:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vabsduh 2, 2, 3
+; CHECK-NEXT: blr
entry:
%res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
-; CHECK-LABEL: @test_half
-; CHECK: vabsduh 2, 2, 3
-; CHECK: blr
}
define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_word:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vabsduw 2, 2, 3
+; CHECK-NEXT: blr
entry:
%res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
-; CHECK-LABEL: @test_word
-; CHECK: vabsduw 2, 2, 3
-; CHECK: blr
}
define <16 x i8> @test_vabsdub(<16 x i8> %0, <16 x i8> %1) {
+; CHECK-LABEL: test_vabsdub:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vabsdub 2, 2, 3
+; CHECK-NEXT: blr
entry:
%2 = zext <16 x i8> %0 to <16 x i32>
%3 = zext <16 x i8> %1 to <16 x i32>
@@ -49,12 +57,13 @@ entry:
%7 = select <16 x i1> %5, <16 x i32> %6, <16 x i32> %4
%8 = trunc <16 x i32> %7 to <16 x i8>
ret <16 x i8> %8
-; CHECK-LABEL: @test_vabsdub
-; CHECK: vabsdub 2, 2, 3
-; CHECK: blr
}
define <8 x i16> @test_vabsduh(<8 x i16> %0, <8 x i16> %1) {
+; CHECK-LABEL: test_vabsduh:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vabsduh 2, 2, 3
+; CHECK-NEXT: blr
entry:
%2 = zext <8 x i16> %0 to <8 x i32>
%3 = zext <8 x i16> %1 to <8 x i32>
@@ -64,19 +73,19 @@ entry:
%7 = select <8 x i1> %5, <8 x i32> %6, <8 x i32> %4
%8 = trunc <8 x i32> %7 to <8 x i16>
ret <8 x i16> %8
-; CHECK-LABEL: @test_vabsduh
-; CHECK: vabsduh 2, 2, 3
-; CHECK: blr
}
define <4 x i32> @test_vabsduw(<4 x i32> %0, <4 x i32> %1) {
+; CHECK-LABEL: test_vabsduw:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvnegsp 35, 35
+; CHECK-NEXT: xvnegsp 34, 34
+; CHECK-NEXT: vabsduw 2, 2, 3
+; CHECK-NEXT: blr
entry:
%2 = sub nsw <4 x i32> %0, %1
%3 = icmp slt <4 x i32> %2, zeroinitializer
%4 = sub nsw <4 x i32> zeroinitializer, %2
%5 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %2
ret <4 x i32> %5
-; CHECK-LABEL: @test_vabsduw
-; CHECK: vabsduw 2, 2, 3
-; CHECK: blr
}
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