[llvm] 188ec33 - [llvm] Use llvm::bit_width (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 21 14:48:39 PST 2023
Author: Kazu Hirata
Date: 2023-01-21T14:48:32-08:00
New Revision: 188ec33726b0502155a218a22304bb79cd02c876
URL: https://github.com/llvm/llvm-project/commit/188ec33726b0502155a218a22304bb79cd02c876
DIFF: https://github.com/llvm/llvm-project/commit/188ec33726b0502155a218a22304bb79cd02c876.diff
LOG: [llvm] Use llvm::bit_width (NFC)
Added:
Modified:
llvm/lib/Analysis/ValueTracking.cpp
llvm/lib/Support/NativeFormatting.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
llvm/lib/Target/XCore/XCoreInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 11427408aa12..260d27b99064 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -1769,7 +1769,7 @@ static void computeKnownBitsFromOperator(const Operator *I,
break;
}
- unsigned FirstZeroHighBit = 32 - countLeadingZeros(*VScaleMax);
+ unsigned FirstZeroHighBit = llvm::bit_width(*VScaleMax);
if (FirstZeroHighBit < BitWidth)
Known.Zero.setBitsFrom(FirstZeroHighBit);
diff --git a/llvm/lib/Support/NativeFormatting.cpp b/llvm/lib/Support/NativeFormatting.cpp
index fb02de792cb6..6e8137c405b8 100644
--- a/llvm/lib/Support/NativeFormatting.cpp
+++ b/llvm/lib/Support/NativeFormatting.cpp
@@ -141,7 +141,7 @@ void llvm::write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style,
size_t W = std::min(kMaxWidth, Width.value_or(0u));
- unsigned Nibbles = (64 - countLeadingZeros(N) + 3) / 4;
+ unsigned Nibbles = (llvm::bit_width(N) + 3) / 4;
bool Prefix = (Style == HexPrintStyle::PrefixLower ||
Style == HexPrintStyle::PrefixUpper);
bool Upper =
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 514b3238547c..9fe27c4c2077 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3356,7 +3356,7 @@ bool AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic(
Register TmpReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
if (!loadInputValue(TmpReg, B, ArgType))
return false;
- B.buildAssertZExt(DstReg, TmpReg, 32 - countLeadingZeros(MaxID));
+ B.buildAssertZExt(DstReg, TmpReg, llvm::bit_width(MaxID));
}
MI.eraseFromParent();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 3504a0269e82..3889c70967b0 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6829,8 +6829,7 @@ SDValue SITargetLowering::lowerWorkitemID(SelectionDAG &DAG, SDValue Op,
return Val;
// Preserve the known bits after expansion to a copy.
- EVT SmallVT =
- EVT::getIntegerVT(*DAG.getContext(), 32 - countLeadingZeros(MaxID));
+ EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), llvm::bit_width(MaxID));
return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Val,
DAG.getValueType(SmallVT));
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9949ea13ef8f..aa4b8fec6a9c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14754,7 +14754,7 @@ static SDValue PerformBFICombine(SDNode *N, SelectionDAG &DAG) {
return SDValue();
unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
unsigned LSB = countTrailingZeros(~InvMask);
- unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
+ unsigned Width = llvm::bit_width<unsigned>(~InvMask) - LSB;
assert(Width <
static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
"undefined behavior");
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
index d9c5b24ff13d..9f275145adfd 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
@@ -740,7 +740,7 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
const MCOperand &MO = MI->getOperand(OpNum);
uint32_t v = ~MO.getImm();
int32_t lsb = countTrailingZeros(v);
- int32_t width = (32 - countLeadingZeros(v)) - lsb;
+ int32_t width = llvm::bit_width(v) - lsb;
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
<< '#' << width << markup(">");
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
index 50f416b23db2..4686bb0b4509 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
@@ -110,7 +110,7 @@ void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) {
while (Regs) {
// Now look for a run of set bits. Remember the MSB and LSB of the run.
- auto RangeMSB = 32 - countLeadingZeros(Regs);
+ auto RangeMSB = llvm::bit_width(Regs);
auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
auto RangeLSB = RangeMSB - RangeLen;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index bebb4ae0c820..28244728f656 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2375,12 +2375,12 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
return false;
break;
case RISCV::ANDI:
- if (Bits >= (64 - countLeadingZeros(User->getConstantOperandVal(1))))
+ if (Bits >= (unsigned)llvm::bit_width(User->getConstantOperandVal(1)))
break;
goto RecCheck;
case RISCV::ORI: {
uint64_t Imm = cast<ConstantSDNode>(User->getOperand(1))->getSExtValue();
- if (Bits >= (64 - countLeadingOnes(Imm)))
+ if (Bits >= (unsigned)llvm::bit_width<uint64_t>(~Imm))
break;
[[fallthrough]];
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 158f02a934e0..6494c9a2cd9d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2635,18 +2635,20 @@ bool RISCVInstrInfo::hasAllNBitUsers(const MachineInstr &OrigMI,
break;
Worklist.push_back(std::make_pair(UserMI, Bits));
break;
- case RISCV::ANDI:
- if (Bits >=
- (64 - countLeadingZeros((uint64_t)UserMI->getOperand(2).getImm())))
+ case RISCV::ANDI: {
+ uint64_t Imm = UserMI->getOperand(2).getImm();
+ if (Bits >= (unsigned)llvm::bit_width(Imm))
break;
Worklist.push_back(std::make_pair(UserMI, Bits));
break;
- case RISCV::ORI:
- if (Bits >=
- (64 - countLeadingOnes((uint64_t)UserMI->getOperand(2).getImm())))
+ }
+ case RISCV::ORI: {
+ uint64_t Imm = UserMI->getOperand(2).getImm();
+ if (Bits >= (unsigned)llvm::bit_width<uint64_t>(~Imm))
break;
Worklist.push_back(std::make_pair(UserMI, Bits));
break;
+ }
case RISCV::SLL:
case RISCV::BSET:
diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 3cb806a84ef0..949b88ad8d4e 100644
--- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -63,7 +63,7 @@ namespace {
if (!isMask_32(value)) {
return false;
}
- int msksize = 32 - countLeadingZeros(value);
+ int msksize = llvm::bit_width(value);
return (msksize >= 1 && msksize <= 8) ||
msksize == 16 || msksize == 24 || msksize == 32;
}
@@ -145,9 +145,9 @@ void XCoreDAGToDAGISel::Select(SDNode *N) {
if (immMskBitp(N)) {
// Transformation function: get the size of a mask
// Look for the first non-zero bit
- SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val), dl);
- ReplaceNode(N, CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
- MVT::i32, MskSize));
+ SDValue MskSize = getI32Imm(llvm::bit_width((uint32_t)Val), dl);
+ ReplaceNode(
+ N, CurDAG->getMachineNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize));
return;
}
else if (!isUInt<16>(Val)) {
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td
index f2b42d42b5a6..de1fb60a30f7 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.td
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td
@@ -96,7 +96,7 @@ def msksize_xform : SDNodeXForm<imm, [{
// Transformation function: get the size of a mask
assert(isMask_32(N->getZExtValue()));
// look for the first non-zero bit
- return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()),
+ return getI32Imm(llvm::bit_width((uint32_t)N->getZExtValue()),
SDLoc(N));
}]>;
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