[PATCH] D142288: [X86] Add basic vector handling for ISD::ABDS/ABDU (absolute difference) nodes

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: pengfei, spatel, dmgreen.
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I'm intending to add generic legalization in the future, but for now I've added basic support to targets that have the necessary MIN/MAX support to expand to SUB(MAX(X,Y),MIN(X,Y)).

This exposed a couple of issues with the DAG combines - in particular we need to catch trunc(abs(sub(ext(x),ext(y)))) patterns earlier before the SSE/AVX vector trunc expansion folds trigger.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142288

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/abds-vector-128.ll
  llvm/test/CodeGen/X86/abds-vector-256.ll
  llvm/test/CodeGen/X86/abds-vector-512.ll
  llvm/test/CodeGen/X86/abdu-vector-128.ll
  llvm/test/CodeGen/X86/abdu-vector-256.ll
  llvm/test/CodeGen/X86/abdu-vector-512.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-512.ll

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