[llvm] 42afa16 - [AArch64] Simplify isSeveralBitsExtractOpFromShr (NFC)

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2023-01-21T09:23:39-08:00
New Revision: 42afa168cdcca1d3307b1fe94534fffb269c1265

URL: https://github.com/llvm/llvm-project/commit/42afa168cdcca1d3307b1fe94534fffb269c1265
DIFF: https://github.com/llvm/llvm-project/commit/42afa168cdcca1d3307b1fe94534fffb269c1265.diff

LOG: [AArch64] Simplify isSeveralBitsExtractOpFromShr (NFC)

This patch simplifies isSeveralBitsExtractOpFromShr.

The following statements are equivalent:

  unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm));
  unsigned BitWide = 64 - countLeadingZeros(AndMask >> SrlImm);

Now, consider:

  if (BitWide && isMask_64(AndMask >> SrlImm)) {

When isMask_64 returns true, AndMask >> SrlImm and BitWide must be
nonzero.  Since BitWide does not contribute to narrowing the
condition, we can simplify the condition as:

  if (isMask_64(AndMask >> SrlImm)) {

We can negate the condition for an early exit as recommended by the
LLVM Coding Standards.

Now, all of the following are equivalent if AndMask >> SrlImm is
nonzero:

  MSB = BitWide + SrlImm - 1
  MSB = (64 - countLeadingZero(AndMask >> SrlImm)) + SrlImm - 1
  MSB = (63 - countLeadingZero(AndMask >> SrlImm)) + SrlImm
  MSB = 63 - countLeadingZero(AndMask)
  MSB = 63 ^ countLeadingZero(AndMask)
  MSB = findLastSet(AndMask, ZB_Undefined)

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 018d4f3201c4..eb23599ab3ba 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2195,7 +2195,7 @@ static bool isSeveralBitsExtractOpFromShr(SDNode *N, unsigned &Opc,
   //
   // This gets selected into a single UBFM:
   //
-  // UBFM Value, ShiftImm, BitWide + SrlImm -1
+  // UBFM Value, ShiftImm, findLastSet(MaskImm)
   //
 
   if (N->getOpcode() != ISD::SRL)
@@ -2212,19 +2212,13 @@ static bool isSeveralBitsExtractOpFromShr(SDNode *N, unsigned &Opc,
     return false;
 
   // Check whether we really have several bits extract here.
-  unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm));
-  if (BitWide && isMask_64(AndMask >> SrlImm)) {
-    if (N->getValueType(0) == MVT::i32)
-      Opc = AArch64::UBFMWri;
-    else
-      Opc = AArch64::UBFMXri;
-
-    LSB = SrlImm;
-    MSB = BitWide + SrlImm - 1;
-    return true;
-  }
+  if (!isMask_64(AndMask >> SrlImm))
+    return false;
 
-  return false;
+  Opc = N->getValueType(0) == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
+  LSB = SrlImm;
+  MSB = findLastSet(AndMask, ZB_Undefined);
+  return true;
 }
 
 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,