[PATCH] D141653: [X86] Improve instruction ordering of constant `srl/shl` with `and` to get better and-masks

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll:942
+; LLC-NEXT:    and x8, x8, #0x78
+; LLC-NEXT:    ldr x0, [x9, x8]
 ; LLC-NEXT:    ret
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@t.p.northover the changes to the `DagCombiner` (allowing `shl/shr` to combine through an `and`) seems to cause regression on Aarch64. Going to update with `TargetLowering` flag unless this is in fact preferable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141653/new/

https://reviews.llvm.org/D141653