[PATCH] D142239: [RISCV] Move Processors and Features from RISCV.td to their own files.

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

Seems like a reasonable refactoring to me. Perhaps worth waiting a day or two to check nobody else has strong opinions on this.



================
Comment at: llvm/lib/Target/RISCV/RISCV.td:34
+//===----------------------------------------------------------------------===//
+// RISC-V Scheduler Models
+//===----------------------------------------------------------------------===//
----------------
Nit: would "RISC-V Scheduling Models" be more -inline with usual LLVM terminology? (I _think_ that's what I've seen more commonly, but I could be wrong!)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D142239/new/

https://reviews.llvm.org/D142239