[llvm] e58010f - [RISCV][TableGen] Move XLen detection into getMArch in RISCVTargetDefEmitter. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-01-20T10:16:28-08:00
New Revision: e58010f712ccac83194852fa95ed70ef76ba6a33

URL: https://github.com/llvm/llvm-project/commit/e58010f712ccac83194852fa95ed70ef76ba6a33
DIFF: https://github.com/llvm/llvm-project/commit/e58010f712ccac83194852fa95ed70ef76ba6a33.diff

LOG: [RISCV][TableGen] Move XLen detection into getMArch in RISCVTargetDefEmitter. NFC

We no longer need the XLen in two places. Fold it into the code
that determines the default march.

Added: 
    

Modified: 
    llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Removed: 
    


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diff  --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 90d2b1817050..bfc5a780e23e 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -19,30 +19,23 @@ using namespace llvm;
 
 using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>;
 
-static int getXLen(const Record &Rec) {
-  std::vector<Record *> Features = Rec.getValueAsListOfDefs("Features");
-  if (find_if(Features, [](const Record *R) {
-        return R->getName() == "Feature64Bit";
-      }) != Features.end())
-    return 64;
-
-  return 32;
-}
-
 // We can generate march string from target features as what has been described
 // in RISCV ISA specification (version 20191213) 'Chapter 27. ISA Extension
 // Naming Conventions'.
 //
 // This is almost the same as RISCVFeatures::parseFeatureBits, except that we
 // get feature name from feature records instead of feature bits.
-static std::string getMArch(int XLen, const Record &Rec) {
+static std::string getMArch(const Record &Rec) {
   std::vector<std::string> FeatureVector;
+  int XLen = 32;
 
   // Convert features to FeatureVector.
   for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
     StringRef FeatureName = Feature->getValueAsString("Name");
     if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
       FeatureVector.push_back((Twine("+") + FeatureName).str());
+    else if (FeatureName == "Feature64Bit")
+      XLen = 64;
   }
 
   ISAInfoTy ISAInfo = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
@@ -62,12 +55,11 @@ void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
   OS << "PROC(INVALID, {\"invalid\"}, {\"\"})\n";
   // Iterate on all definition records.
   for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
-    int XLen = getXLen(*Rec);
     std::string MArch = Rec->getValueAsString("DefaultMarch").str();
 
     // Compute MArch from features if we don't specify it.
     if (MArch.empty())
-      MArch = getMArch(XLen, *Rec);
+      MArch = getMArch(*Rec);
 
     OS << "PROC(" << Rec->getName() << ", "
        << "{\"" << Rec->getValueAsString("Name") << "\"}, "