[llvm] 0ccbf91 - [RISCV] Remove Features from CPUInfo in RISCVTargetParser.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-01-20T10:03:37-08:00
New Revision: 0ccbf911668786fbde7e1107c08c3eeef0f1eb4b

URL: https://github.com/llvm/llvm-project/commit/0ccbf911668786fbde7e1107c08c3eeef0f1eb4b
DIFF: https://github.com/llvm/llvm-project/commit/0ccbf911668786fbde7e1107c08c3eeef0f1eb4b.diff

LOG: [RISCV] Remove Features from CPUInfo in RISCVTargetParser.

Instead of having separate feature bits, get information from march.
Invalid is now implied by empty march.
64-bit is now implied by march starting with "rv64".

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D142230

Added: 
    

Modified: 
    llvm/include/llvm/TargetParser/RISCVTargetParser.h
    llvm/lib/TargetParser/RISCVTargetParser.cpp
    llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Removed: 
    


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diff  --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 85819e1e4b7fc..da2ecd8c1339d 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,17 +24,11 @@ namespace RISCV {
 static constexpr unsigned RVVBitsPerBlock = 64;
 
 enum CPUKind : unsigned {
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
+#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
 #define TUNE_PROC(ENUM, NAME) CK_##ENUM,
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };
 
-enum FeatureKind : unsigned {
-  FK_INVALID = 0,
-  FK_NONE = 1,
-  FK_64BIT = 1 << 2,
-};
-
 bool checkCPUKind(CPUKind Kind, bool IsRV64);
 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
 CPUKind parseCPUKind(StringRef CPU);

diff  --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 6ec2892cdae1e..89cd5c082d72d 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -21,14 +21,14 @@ namespace RISCV {
 struct CPUInfo {
   StringLiteral Name;
   CPUKind Kind;
-  unsigned Features;
   StringLiteral DefaultMarch;
-  bool is64Bit() const { return (Features & FK_64BIT); }
+  bool isInvalid() const { return DefaultMarch.empty(); }
+  bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
 };
 
 constexpr CPUInfo RISCVCPUInfo[] = {
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)                              \
-  {NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH},
+#define PROC(ENUM, NAME, DEFAULT_MARCH)                              \
+  {NAME, CK_##ENUM, DEFAULT_MARCH},
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };
 
@@ -50,14 +50,14 @@ bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
 
 CPUKind parseCPUKind(StringRef CPU) {
   return llvm::StringSwitch<CPUKind>(CPU)
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
+#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
       .Default(CK_INVALID);
 }
 
 CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
   return llvm::StringSwitch<CPUKind>(TuneCPU)
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
+#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
 #define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
       .Default(CK_INVALID);
@@ -87,12 +87,12 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
 // Get all features except standard extension feature
 bool getCPUFeaturesExceptStdExt(CPUKind Kind,
                                 std::vector<StringRef> &Features) {
-  unsigned CPUFeatures = RISCVCPUInfo[static_cast<unsigned>(Kind)].Features;
+  const CPUInfo &Info = RISCVCPUInfo[static_cast<unsigned>(Kind)];
 
-  if (CPUFeatures == FK_INVALID)
+  if (Info.isInvalid())
     return false;
 
-  if (CPUFeatures & FK_64BIT)
+  if (Info.is64Bit())
     Features.push_back("+64bit");
   else
     Features.push_back("-64bit");

diff  --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index f513bd426a17a..90d2b18170501 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -54,16 +54,12 @@ static std::string getMArch(int XLen, const Record &Rec) {
   return (*ISAInfo)->toString();
 }
 
-static std::string getEnumFeatures(int XLen) {
-  return XLen == 64 ? "FK_64BIT" : "FK_NONE";
-}
-
 void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
   OS << "#ifndef PROC\n"
-     << "#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)\n"
+     << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
      << "#endif\n\n";
 
-  OS << "PROC(INVALID, {\"invalid\"}, FK_INVALID, {\"\"})\n";
+  OS << "PROC(INVALID, {\"invalid\"}, {\"\"})\n";
   // Iterate on all definition records.
   for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
     int XLen = getXLen(*Rec);
@@ -74,8 +70,7 @@ void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
       MArch = getMArch(XLen, *Rec);
 
     OS << "PROC(" << Rec->getName() << ", "
-       << "{\"" << Rec->getValueAsString("Name") << "\"},"
-       << getEnumFeatures(XLen) << ", "
+       << "{\"" << Rec->getValueAsString("Name") << "\"}, "
        << "{\"" << MArch << "\"})\n";
   }
   OS << "\n#undef PROC\n";