[PATCH] D141017: [MachineCombiner] Use default latency model when no detailed model available

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 20 09:28:53 PST 2023


This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG86eff6be686a: [MachineCombiner] Use default latency model when no detailed model available (authored by reames).
Herald added a subscriber: luke.

Changed prior to commit:
  https://reviews.llvm.org/D141017?vs=486367&id=490892#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141017/new/

https://reviews.llvm.org/D141017

Files:
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
  llvm/test/CodeGen/RISCV/addcarry.ll
  llvm/test/CodeGen/RISCV/addimm-mulimm.ll
  llvm/test/CodeGen/RISCV/alu64.ll
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/div-by-constant.ll
  llvm/test/CodeGen/RISCV/div-pow2.ll
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/iabs.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/neg-abs.ll
  llvm/test/CodeGen/RISCV/rotl-rotr.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
  llvm/test/CodeGen/RISCV/sadd_sat.ll
  llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/select-binop-identity.ll
  llvm/test/CodeGen/RISCV/shadowcallstack.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/ssub_sat.ll
  llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
  llvm/test/CodeGen/RISCV/uadd_sat.ll
  llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/RISCV/unaligned-load-store.ll
  llvm/test/CodeGen/RISCV/urem-lkk.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/usub_sat.ll
  llvm/test/CodeGen/RISCV/usub_sat_plus.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/RISCV/xaluo.ll
  llvm/test/CodeGen/X86/abdu-vector-128.ll
  llvm/test/CodeGen/X86/add-sub-bool.ll
  llvm/test/CodeGen/X86/alias-static-alloca.ll
  llvm/test/CodeGen/X86/avx-vinsertf128.ll
  llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
  llvm/test/CodeGen/X86/avx512-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/avx512-intrinsics.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
  llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
  llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
  llvm/test/CodeGen/X86/avx512fp16-mov.ll
  llvm/test/CodeGen/X86/avx512fp16-mscatter.ll
  llvm/test/CodeGen/X86/avx512vl-intrinsics.ll
  llvm/test/CodeGen/X86/bmi-out-of-order.ll
  llvm/test/CodeGen/X86/combine-add.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/X86/divide-by-constant.ll
  llvm/test/CodeGen/X86/divmod128.ll
  llvm/test/CodeGen/X86/fold-add.ll
  llvm/test/CodeGen/X86/fold-masked-merge.ll
  llvm/test/CodeGen/X86/fold-tied-op.ll
  llvm/test/CodeGen/X86/h-registers-1.ll
  llvm/test/CodeGen/X86/hipe-cc.ll
  llvm/test/CodeGen/X86/hipe-cc64.ll
  llvm/test/CodeGen/X86/horizontal-reduce-add.ll
  llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
  llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
  llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
  llvm/test/CodeGen/X86/horizontal-sum.ll
  llvm/test/CodeGen/X86/icmp-shift-opt.ll
  llvm/test/CodeGen/X86/imul.ll
  llvm/test/CodeGen/X86/lea-opt-cse4.ll
  llvm/test/CodeGen/X86/lea-opt2.ll
  llvm/test/CodeGen/X86/logic-shift.ll
  llvm/test/CodeGen/X86/machine-cp.ll
  llvm/test/CodeGen/X86/madd.ll
  llvm/test/CodeGen/X86/masked_gather.ll
  llvm/test/CodeGen/X86/masked_gather_scatter.ll
  llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
  llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
  llvm/test/CodeGen/X86/midpoint-int.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/mul-constant-i64.ll
  llvm/test/CodeGen/X86/mul-constant-result.ll
  llvm/test/CodeGen/X86/mul-i1024.ll
  llvm/test/CodeGen/X86/mul-i256.ll
  llvm/test/CodeGen/X86/mul-i512.ll
  llvm/test/CodeGen/X86/mul128.ll
  llvm/test/CodeGen/X86/mul64.ll
  llvm/test/CodeGen/X86/muloti.ll
  llvm/test/CodeGen/X86/optimize-max-0.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/pr34080-2.ll
  llvm/test/CodeGen/X86/ptest.ll
  llvm/test/CodeGen/X86/rev16.ll
  llvm/test/CodeGen/X86/rotate-multi.ll
  llvm/test/CodeGen/X86/sad.ll
  llvm/test/CodeGen/X86/setcc-wide-types.ll
  llvm/test/CodeGen/X86/shift-combine.ll
  llvm/test/CodeGen/X86/smul-with-overflow.ll
  llvm/test/CodeGen/X86/smul_fix.ll
  llvm/test/CodeGen/X86/smul_fix_sat.ll
  llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/X86/sse-regcall.ll
  llvm/test/CodeGen/X86/stack-clash-large.ll
  llvm/test/CodeGen/X86/statepoint-live-in.ll
  llvm/test/CodeGen/X86/statepoint-regs.ll
  llvm/test/CodeGen/X86/swift-return.ll
  llvm/test/CodeGen/X86/umul-with-overflow.ll
  llvm/test/CodeGen/X86/umul_fix.ll
  llvm/test/CodeGen/X86/umul_fix_sat.ll
  llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/X86/umulo-64-legalisation-lowering.ll
  llvm/test/CodeGen/X86/urem-seteq-nonzero.ll
  llvm/test/CodeGen/X86/v8i1-masks.ll
  llvm/test/CodeGen/X86/vec_smulo.ll
  llvm/test/CodeGen/X86/vec_umulo.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
  llvm/test/CodeGen/X86/vector-pcmp.ll
  llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
  llvm/test/CodeGen/X86/vector-reduce-add-sext.ll
  llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
  llvm/test/CodeGen/X86/vector-reduce-add.ll
  llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll
  llvm/test/CodeGen/X86/vector-reduce-and.ll
  llvm/test/CodeGen/X86/vector-reduce-mul.ll
  llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
  llvm/test/CodeGen/X86/vector-reduce-or.ll
  llvm/test/CodeGen/X86/vector-reduce-smax.ll
  llvm/test/CodeGen/X86/vector-reduce-smin.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-reduce-umin.ll
  llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-xor.ll
  llvm/test/CodeGen/X86/vector-trunc-math.ll
  llvm/test/CodeGen/X86/vector-trunc-packus.ll
  llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
  llvm/test/CodeGen/X86/win-smallparams.ll
  llvm/test/CodeGen/X86/x86-32-vector-calling-conv.ll
  llvm/test/CodeGen/X86/x86-interleaved-access.ll
  llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll
  llvm/test/CodeGen/X86/xmulo.ll



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