[PATCH] D142231: [AMDGPU][AsmParser] Forbid optional SMRD offsets on GFX6/GFX7.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev created this revision.
kosarev added reviewers: dp, arsenm, rampitec, foad.
Herald added subscribers: StephenFan, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
Herald added a project: All.
kosarev requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142231

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/SMInstructions.td
  llvm/test/MC/AMDGPU/gfx7_asm_err.s


Index: llvm/test/MC/AMDGPU/gfx7_asm_err.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AMDGPU/gfx7_asm_err.s
@@ -0,0 +1,7 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --implicit-check-not=error:
+
+//==============================================================================
+// operands are not valid for this GPU or mode
+
+s_load_dword s1, s[2:3]
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
Index: llvm/lib/Target/AMDGPU/SMInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SMInstructions.td
+++ llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -6,8 +6,11 @@
 //
 //===----------------------------------------------------------------------===//
 
-def smrd_offset_8 : NamedOperandU32<"SMRDOffset8",
-                                  NamedMatchClass<"SMRDOffset8">> {
+def SMRDOffset8Class : NamedMatchClass<"SMRDOffset8", 0> {
+  let ParserMethod = "";
+}
+
+def smrd_offset_8 : NamedOperandU32<"SMRDOffset8", SMRDOffset8Class> {
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
@@ -756,8 +759,12 @@
 // CI
 //===----------------------------------------------------------------------===//
 
+def SMRDLiteralOffsetClass : NamedMatchClass<"SMRDLiteralOffset", 0> {
+  let ParserMethod = "";
+}
+
 def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
-                                          NamedMatchClass<"SMRDLiteralOffset">> {
+                                          SMRDLiteralOffsetClass> {
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
Index: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1743,9 +1743,7 @@
 
   AMDGPUOperand::Ptr defaultCPol() const;
 
-  AMDGPUOperand::Ptr defaultSMRDOffset8() const;
   AMDGPUOperand::Ptr defaultSMEMOffset() const;
-  AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
   AMDGPUOperand::Ptr defaultFlatOffset() const;
 
   OperandMatchResultTy parseOModOperand(OperandVector &Operands);
@@ -7956,18 +7954,10 @@
   return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
 }
 
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset8() const {
-  return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
-}
-
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMEMOffset() const {
   return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
 }
 
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDLiteralOffset() const {
-  return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
-}
-
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFlatOffset() const {
   return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
 }


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