[llvm] b3154d0 - [ARM][AArch64] Switch to generic MEMBARRIER node
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 20 08:54:42 PST 2023
Author: Philip Reames
Date: 2023-01-20T08:54:34-08:00
New Revision: b3154d08e948c37872bf053f90b6728e7d39039b
URL: https://github.com/llvm/llvm-project/commit/b3154d08e948c37872bf053f90b6728e7d39039b
DIFF: https://github.com/llvm/llvm-project/commit/b3154d08e948c37872bf053f90b6728e7d39039b.diff
LOG: [ARM][AArch64] Switch to generic MEMBARRIER node
This change switches both targets from using target specific CompilerBarrier nodes to the recently introduced generic MEMBARRIER instruction.
A couple things to call out.
First, this changes the assembly comment printed. I'm not sure this matters, but if it does, we can simply drop this patch. This is a minor clean up at best.
Second, the ordering operand on the target instruction appears to be unused. We could easily add ordering to the generic instruction, but since we don't seem to have a motivating case in tree, I simply dropped the ordering when selecting to the generic instruction.
Differential Revision: https://reviews.llvm.org/D141513
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrAtomics.td
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/test/CodeGen/AArch64/fence-singlethread.ll
llvm/test/CodeGen/ARM/fence-singlethread.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index cc3d5a968b55..64629eec2289 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -13,9 +13,8 @@
//===----------------------------------
// Atomic fences
//===----------------------------------
-let AddedComplexity = 15, Size = 0 in
-def CompilerBarrier : Pseudo<(outs), (ins i32imm:$ordering),
- [(atomic_fence timm:$ordering, 0)]>, Sched<[]>;
+let AddedComplexity = 15 in
+def : Pat<(atomic_fence (timm), 0), (MEMBARRIER)>;
def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index ea3403aa799a..58e89010c139 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2351,8 +2351,7 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) {
}
case TargetOpcode::G_FENCE: {
if (I.getOperand(1).getImm() == 0)
- BuildMI(MBB, I, MIMetadata(I), TII.get(AArch64::CompilerBarrier))
- .addImm(I.getOperand(0).getImm());
+ BuildMI(MBB, I, MIMetadata(I), TII.get(TargetOpcode::MEMBARRIER));
else
BuildMI(MBB, I, MIMetadata(I), TII.get(AArch64::DMB))
.addImm(I.getOperand(0).getImm() == 4 ? 0x9 : 0xb);
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 074cde6c0b7e..6ff5459fe026 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -337,12 +337,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
}
}
- if (Opcode == AArch64::CompilerBarrier) {
- O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
- printAnnotation(O, Annot);
- return;
- }
-
if (Opcode == AArch64::SPACE) {
O << '\t' << MAI.getCommentString() << " SPACE "
<< MI->getOperand(1).getImm();
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index 409316f9e3a0..e482ab731012 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -677,9 +677,7 @@ void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
return;
}
- if (MI.getOpcode() == AArch64::CompilerBarrier ||
- MI.getOpcode() == AArch64::SPACE) {
- // CompilerBarrier just prevents the compiler from reordering accesses, and
+ if (MI.getOpcode() == AArch64::SPACE) {
// SPACE just increases basic block size, in both cases no actual code.
return;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 20d4db8410b4..f5415c5b5895 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -6486,13 +6486,7 @@ def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
NoItinerary, []>, Sched<[]>;
}
-def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary,
- [(atomic_fence timm:$ordering, 0)]> {
- let hasSideEffects = 1;
- let Size = 0;
- let AsmString = "@ COMPILER BARRIER";
- let hasNoSchedulingInfo = 1;
-}
+def : Pat<(atomic_fence (timm), 0), (MEMBARRIER)>;
//===----------------------------------------------------------------------===//
// Instructions used for emitting unwind opcodes on Windows.
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 0a440555a0c4..3baac6b233c4 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -119,8 +119,7 @@ def : InstRW<[WriteNoop], (instregex "(t)?BKPT$", "(t2)?CDP(2)?$",
"(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
"(t2)?RFE(DA|DB|IA|IB)", "(t)?SETEND", "(t2)?SETPAN", "(t2)?SMC", "SPACE",
"(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "(t2|t)?UDF$", "t2DCPS", "t2SG",
- "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "CompilerBarrier",
- "t__brkdiv0")>;
+ "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "t__brkdiv0")>;
def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>;
diff --git a/llvm/test/CodeGen/AArch64/fence-singlethread.ll b/llvm/test/CodeGen/AArch64/fence-singlethread.ll
index b8776062119c..f36d28926acb 100644
--- a/llvm/test/CodeGen/AArch64/fence-singlethread.ll
+++ b/llvm/test/CodeGen/AArch64/fence-singlethread.ll
@@ -9,12 +9,12 @@
define void @fence_singlethread() {
; LINUX-LABEL: fence_singlethread:
; LINUX-NOT: dmb
-; LINUX: // COMPILER BARRIER
+; LINUX: //MEMBARRIER
; LINUX-NOT: dmb
; IOS-LABEL: fence_singlethread:
; IOS-NOT: dmb
-; IOS: ; COMPILER BARRIER
+; IOS: ;MEMBARRIER
; IOS-NOT: dmb
fence syncscope("singlethread") seq_cst
diff --git a/llvm/test/CodeGen/ARM/fence-singlethread.ll b/llvm/test/CodeGen/ARM/fence-singlethread.ll
index 536b6cc7c9d0..3bbc384f5aad 100644
--- a/llvm/test/CodeGen/ARM/fence-singlethread.ll
+++ b/llvm/test/CodeGen/ARM/fence-singlethread.ll
@@ -8,7 +8,7 @@
define void @fence_singlethread() {
; CHECK-LABEL: fence_singlethread:
; CHECK-NOT: dmb
-; CHECK: @ COMPILER BARRIER
+; CHECK: @MEMBARRIER
; CHECK-NOT: dmb
fence syncscope("singlethread") seq_cst
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