[llvm] 9f85447 - [DebugInfo] Store instr-ref mode of MachineFunction in member
Jeremy Morse via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 20 06:47:30 PST 2023
Author: Jeremy Morse
Date: 2023-01-20T14:47:11Z
New Revision: 9f8544713ad8e57fb74cbfce3fbc7fff523e549f
URL: https://github.com/llvm/llvm-project/commit/9f8544713ad8e57fb74cbfce3fbc7fff523e549f
DIFF: https://github.com/llvm/llvm-project/commit/9f8544713ad8e57fb74cbfce3fbc7fff523e549f.diff
LOG: [DebugInfo] Store instr-ref mode of MachineFunction in member
Add a flag state (and a MIR key) to MachineFunctions indicating whether they
contain instruction referencing debug-info or not. Whether DBG_VALUEs or
DBG_INSTR_REFs are used needs to be determined by LiveDebugValues at least, and
using the current optimisation level as a proxy is proving unreliable.
Test updates are purely adding the flag to tests, in a couple of cases it
involves separating out VarLocBasedLDV/InstrRefBasedLDV tests into separate
files, as they can no longer share the same input.
Differential Revision: https://reviews.llvm.org/D141387
Added:
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir
Modified:
llvm/include/llvm/CodeGen/FastISel.h
llvm/include/llvm/CodeGen/MIRYamlMapping.h
llvm/include/llvm/CodeGen/MachineFunction.h
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir
llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir
llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir
llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir
llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir
llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir
llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
llvm/test/DebugInfo/X86/instr-ref-flag.ll
llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h
index fd779d28ae238..d25776e5eff16 100644
--- a/llvm/include/llvm/CodeGen/FastISel.h
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -213,7 +213,6 @@ class FastISel {
const TargetRegisterInfo &TRI;
const TargetLibraryInfo *LibInfo;
bool SkipTargetIndependentISel;
- bool UseInstrRefDebugInfo = false;
/// The position of the last instruction for materializing constants
/// for use in the current block. It resets to EmitStartPt when it makes sense
@@ -320,12 +319,6 @@ class FastISel {
/// Reset InsertPt to the given old insert position.
void leaveLocalValueArea(SavePoint Old);
- /// Signal whether instruction referencing variable locations are desired for
- /// this function's debug-info.
- void useInstrRefDebugInfo(bool Flag) {
- UseInstrRefDebugInfo = Flag;
- }
-
protected:
explicit FastISel(FunctionLoweringInfo &FuncInfo,
const TargetLibraryInfo *LibInfo,
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index ba6b64d0a8482..62911c2bd7411 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -707,6 +707,7 @@ struct MachineFunction {
bool FailsVerification = false;
bool TracksDebugUserValues = false;
+ bool UseDebugInstrRef = false;
std::vector<VirtualRegisterDefinition> VirtualRegisters;
std::vector<MachineFunctionLiveIn> LiveIns;
std::optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
@@ -741,6 +742,7 @@ template <> struct MappingTraits<MachineFunction> {
YamlIO.mapOptional("hasEHCatchret", MF.HasEHCatchret, false);
YamlIO.mapOptional("hasEHScopes", MF.HasEHScopes, false);
YamlIO.mapOptional("hasEHFunclets", MF.HasEHFunclets, false);
+ YamlIO.mapOptional("debugInstrRef", MF.UseDebugInstrRef, false);
YamlIO.mapOptional("failsVerification", MF.FailsVerification, false);
YamlIO.mapOptional("tracksDebugUserValues", MF.TracksDebugUserValues,
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 31aaedd8f65e1..220d18d15821c 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -527,6 +527,10 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
/// during register allocation. See DebugPHIRegallocPos.
DenseMap<unsigned, DebugPHIRegallocPos> DebugPHIPositions;
+ /// Flag for whether this function contains DBG_VALUEs (false) or
+ /// DBG_INSTR_REF (true).
+ bool UseDebugInstrRef = false;
+
/// Create a substitution between one <instr,operand> value to a
diff erent,
/// new value.
void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair,
@@ -567,10 +571,17 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
/// (or DBG_PHI).
void finalizeDebugInstrRefs();
- /// Returns true if the function's variable locations should be tracked with
+ /// Determine whether, in the current machine configuration, we should use
+ /// instruction referencing or not.
+ bool shouldUseDebugInstrRef() const;
+
+ /// Returns true if the function's variable locations are tracked with
/// instruction referencing.
bool useDebugInstrRef() const;
+ /// Set whether this function will use instruction referencing or not.
+ void setUseDebugInstrRef(bool UseInstrRef);
+
/// A reserved operand number representing the instructions memory operand,
/// for instructions that have a stack spill fused into them.
const static unsigned int DebugOperandMemNumber;
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index c8fff08158493..491c187ef6e4f 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -293,9 +293,6 @@ class SelectionDAG {
/// benefits (see discussion with @thakis in D120714).
uint16_t NextPersistentId = 0;
- /// Are instruction referencing variable locations desired for this function?
- bool UseInstrRefDebugInfo = false;
-
public:
/// Clients of various APIs that cause global effects on
/// the DAG can optionally implement this interface. This allows the clients
@@ -1901,16 +1898,6 @@ class SelectionDAG {
/// function mirrors \c llvm::salvageDebugInfo.
void salvageDebugInfo(SDNode &N);
- /// Signal whether instruction referencing variable locations are desired for
- /// this function's debug-info.
- void useInstrRefDebugInfo(bool Flag) {
- UseInstrRefDebugInfo = Flag;
- }
-
- bool getUseInstrRefDebugInfo() const {
- return UseInstrRefDebugInfo;
- }
-
void dump() const;
/// In most cases this function returns the ABI alignment for a given type,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index d690a186f3695..b7c5bec910516 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -56,7 +56,6 @@ class SelectionDAGISel : public MachineFunctionPass {
const TargetLowering *TLI;
bool FastISelFailed;
SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
- bool UseInstrRefDebugInfo = false;
/// Current optimization remark emitter.
/// Used to report things like combines and FastISel failures.
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f13116e169f35..a20c2bfe6c0fd 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -443,6 +443,9 @@ void MIRParserImpl::setupDebugValueTracking(
MF.makeDebugValueSubstitution({Sub.SrcInst, Sub.SrcOp},
{Sub.DstInst, Sub.DstOp}, Sub.Subreg);
}
+
+ // Flag for whether we're supposed to be using DBG_INSTR_REF.
+ MF.setUseDebugInstrRef(YamlMF.UseDebugInstrRef);
}
bool
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 0f4a8a280bc8e..0a4b28ac79a73 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -200,6 +200,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
YamlMF.HasEHCatchret = MF.hasEHCatchret();
YamlMF.HasEHScopes = MF.hasEHScopes();
YamlMF.HasEHFunclets = MF.hasEHFunclets();
+ YamlMF.UseDebugInstrRef = MF.useDebugInstrRef();
YamlMF.Legalized = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Legalized);
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index a6fd3a8870729..59e6647fa643d 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1195,7 +1195,7 @@ void MachineFunction::finalizeDebugInstrRefs() {
}
}
-bool MachineFunction::useDebugInstrRef() const {
+bool MachineFunction::shouldUseDebugInstrRef() const {
// Disable instr-ref at -O0: it's very slow (in compile time). We can still
// have optimized code inlined into this unoptimized code, however with
// fewer and less aggressive optimizations happening, coverage and accuracy
@@ -1213,6 +1213,14 @@ bool MachineFunction::useDebugInstrRef() const {
return false;
}
+bool MachineFunction::useDebugInstrRef() const {
+ return UseDebugInstrRef;
+}
+
+void MachineFunction::setUseDebugInstrRef(bool Use) {
+ UseDebugInstrRef = Use;
+}
+
// Use one million as a high / reserved number.
const unsigned MachineFunction::DebugOperandMemNumber = 1000000;
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 36c749ceb5a1d..08e55e65d72d0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1247,7 +1247,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
if (Op) {
assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) &&
"Expected inlined-at fields to agree");
- if (UseInstrRefDebugInfo && Op->isReg()) {
+ if (FuncInfo.MF->useDebugInstrRef() && Op->isReg()) {
// If using instruction referencing, produce this as a DBG_INSTR_REF,
// to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
// the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
@@ -1309,7 +1309,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
.addMetadata(DI->getExpression());
} else if (Register Reg = lookUpRegForValue(V)) {
// FIXME: This does not handle register-indirect values at offset 0.
- if (!UseInstrRefDebugInfo) {
+ if (!FuncInfo.MF->useDebugInstrRef()) {
bool IsIndirect = false;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II, IsIndirect,
Reg, DI->getVariable(), DI->getExpression());
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 2a05b0f664a7f..e39b2c26641b8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -1395,12 +1395,11 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
/// at the given position in the given block.
InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
- MachineBasicBlock::iterator insertpos,
- bool UseInstrRefDebugInfo)
+ MachineBasicBlock::iterator insertpos)
: MF(mbb->getParent()), MRI(&MF->getRegInfo()),
TII(MF->getSubtarget().getInstrInfo()),
TRI(MF->getSubtarget().getRegisterInfo()),
TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
InsertPos(insertpos) {
- EmitDebugInstrRefs = UseInstrRefDebugInfo;
+ EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef();
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
index 909d1a95560d9..959bce31c8b27 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
@@ -156,8 +156,7 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
/// at the given position in the given block.
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
- MachineBasicBlock::iterator insertpos,
- bool UseInstrRefDebugInfo);
+ MachineBasicBlock::iterator insertpos);
private:
void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index ac65ceed20ed7..df7cfd500649e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -778,8 +778,7 @@ void ScheduleDAGLinearize::Schedule() {
MachineBasicBlock*
ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
- InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos,
- DAG->getUseInstrRefDebugInfo());
+ InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);
DenseMap<SDValue, Register> VRBaseMap;
LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; });
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 239d5722e115e..a4b16334506fe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -848,8 +848,7 @@ EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap,
/// not necessarily refer to returned BB. The emitter may split blocks.
MachineBasicBlock *ScheduleDAGSDNodes::
EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
- InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos,
- DAG->getUseInstrRefDebugInfo());
+ InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);
DenseMap<SDValue, Register> VRBaseMap;
DenseMap<SUnit*, Register> CopyVRBaseMap;
SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 30108f1c23ad7..902f461155574 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -392,8 +392,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// Decide what flavour of variable location debug-info will be used, before
// we change the optimisation level.
- UseInstrRefDebugInfo = mf.useDebugInstrRef();
- CurDAG->useInstrRefDebugInfo(UseInstrRefDebugInfo);
+ bool InstrRef = mf.shouldUseDebugInstrRef();
+ mf.setUseDebugInstrRef(InstrRef);
// Reset the target options before resetting the optimization
// level below.
@@ -546,7 +546,6 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
LiveInMap.insert(LI);
// Insert DBG_VALUE instructions for function arguments to the entry block.
- bool InstrRef = MF->useDebugInstrRef();
for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
MachineInstr *MI = FuncInfo->ArgDbgValues[e - i - 1];
assert(MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
@@ -624,7 +623,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// For debug-info, in instruction referencing mode, we need to perform some
// post-isel maintenence.
- if (UseInstrRefDebugInfo)
+ if (MF->useDebugInstrRef())
MF->finalizeDebugInstrRefs();
// Determine if there are any calls in this machine function.
@@ -1380,8 +1379,6 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
if (TM.Options.EnableFastISel) {
LLVM_DEBUG(dbgs() << "Enabling fast-isel\n");
FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
- if (FastIS)
- FastIS->useInstrRefDebugInfo(UseInstrRefDebugInfo);
}
ReversePostOrderTraversal<const Function*> RPOT(&Fn);
diff --git a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
index 6f8a05d302a4a..6bb05dea4b5e1 100644
--- a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
+++ b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
@@ -32,6 +32,7 @@
---
name: foo
tracksRegLiveness: true
+debugInstrRef: true
debugValueSubstitutions:
- { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir b/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
index 9f88a423ff390..563c7258543cf 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
@@ -73,6 +73,7 @@ name: c
alignment: 16
tracksRegLiveness: true
tracksDebugUserValues: true
+debugInstrRef: true
frameInfo:
maxAlignment: 4
machineFunctionInfo: {}
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
index d1431ab0d34ff..9eb7345f44179 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
@@ -50,6 +50,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$edi' }
frameInfo:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
index 08e9b302221be..43603b88c4e50 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
@@ -86,6 +86,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
index 7255788c8b540..945574cb3cd39 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
@@ -45,6 +45,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
index e06fa4335ad08..9601aad77d93c 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
@@ -98,6 +98,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
index a9cb23ffbc12f..8d7a74795ec2e 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
@@ -99,6 +99,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
index 352e41d00203d..0253c95cc1324 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
@@ -138,6 +138,7 @@
name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir
index abd8710615745..512a10d512a43 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir
@@ -99,6 +99,7 @@
name: _Z3foo10NonTrivial
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
tracksDebugUserValues: true
liveins:
- { reg: '$rdi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
index 159a70c82bcdf..59d8e735c678f 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
@@ -178,6 +178,7 @@
name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir b/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
index b045cbc784fcd..53312f93772a2 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
@@ -2,10 +2,12 @@
#
# REQUIRES: x86-registered-target
#
+# CHECK: debugInstrRef: true
# CHECK: MOV64rr $rdi, debug-instr-number 1
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir
index 72f9d9686e64a..7ff40aa28b954 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir
@@ -155,6 +155,7 @@ name: _Z3fooii
alignment: 16
tracksRegLiveness: true
tracksDebugUserValues: true
+debugInstrRef: true
registers: []
liveins:
- { reg: '$edi', virtual-reg: '' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
index b543469a45985..1a48ab5ed230d 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
@@ -37,6 +37,7 @@
...
---
name: _Z8bb_to_bb
+debugInstrRef: true
debugValueSubstitutions:
- { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
index 593a9ee7a949b..12ff645467e8c 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
@@ -31,6 +31,7 @@
...
---
name: _Z8bb_to_bb
+debugInstrRef: true
debugValueSubstitutions:
- { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
index 83c92c09df1a5..33e3be7634c58 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
@@ -50,6 +50,7 @@
...
---
name: _Z8bb_to_bb
+debugInstrRef: true
stack:
- { id: 0, type: spill-slot, offset: -12, size: 4, alignment: 4 }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
index 0270f8d0cfe84..d02a4062d9b72 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
@@ -29,6 +29,7 @@
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
stack:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
index f75de1102c2c6..7c2111977fe76 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
@@ -31,6 +31,7 @@
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
debugValueSubstitutions:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
index 54ab5b06735ef..0ef750f94b867 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
@@ -57,6 +57,7 @@
name: _ZNK4llvm5APInt5magicEv
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr64 }
- { id: 1, class: gr32 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir
index ee004e0354fd4..8d506fa7065bd 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir
@@ -49,6 +49,7 @@
---
name: beans
tracksRegLiveness: True
+debugInstrRef: true
body: |
bb.0:
liveins: $edi
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
index a90512f3245b2..f0af938040483 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
@@ -68,6 +68,7 @@
---
name: foo
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr32, preferred-register: '' }
- { id: 1, class: fr32, preferred-register: '' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
index 420edb5088861..c05161eda8073 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
@@ -36,6 +36,7 @@
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
debugValueSubstitutions:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir b/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
index 5ade1830995b2..782ddf895a8c6 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
@@ -28,6 +28,7 @@
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir b/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
index b1d5c03d68b8e..917d921a50606 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
@@ -28,6 +28,7 @@
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
index cb150cb0fd8c1..9d11eb77eec26 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
@@ -86,6 +86,7 @@
name: main
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rsi' }
frameInfo:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
index 0a2a375d7c781..a2f991074671e 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
@@ -91,6 +91,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$edi', virtual-reg: '%3' }
- { reg: '$esi', virtual-reg: '%4' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
index 95ef05e765964..b4172bd5f008a 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
@@ -100,6 +100,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '%3' }
- { reg: '$rsi', virtual-reg: '%5' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
index 1378224354114..d59333e73fbce 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
@@ -58,6 +58,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr16 }
- { id: 1, class: gr32 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
index 529259716d3a4..ab2647d3b45a1 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
@@ -59,6 +59,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr8 }
- { id: 1, class: gr32_abcd }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
index f6cf169ffe2ed..0fe80980e4e6f 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
@@ -53,6 +53,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
index 720cc609ccbaa..2a031b295a1e1 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
@@ -82,6 +82,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir b/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
index 4c1b3cca45692..4a6cda54d0fe7 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
@@ -77,6 +77,7 @@
name: bees
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir b/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir
index 7cde4dec4b481..aadfd3c7448bf 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir
@@ -46,6 +46,7 @@
name: _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir b/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir
index fa5fccfddcd7e..35495634d42aa 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir
@@ -43,6 +43,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
frameInfo:
stackSize: 24
offsetAdjustment: -24
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
index c247004368837..8f43a55b34001 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
@@ -2,10 +2,6 @@
# RUN: -experimental-debug-variable-locations=true \
# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \
# RUN: --check-prefixes=CHECK,COMMON
-# RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - \
-# RUN: -experimental-debug-variable-locations=false \
-# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \
-# RUN: --check-prefixes=VARLOC,COMMON
#
# This test is designed to stimulate a simplification of variable-value
# propagation in InstrRefBasedLDV. When we only have a single assignment of
@@ -57,13 +53,14 @@
#
## VarLocBasedLDV will take the DBG_VALUE in the assignment block, propagate
## to bb.3, but not into bb.4 because of the intervening out-of-scope block.
+## Disabled actual testing of this because it's just for comparison purposes.
#
-# VARLOC-LABEL: bb.1:
-# VARLOC: DBG_VALUE
-# VARLOC-LABEL: bb.2:
+# varloc-label: bb.1:
+# varloc: DBG_VALUE
+# varloc-label: bb.2:
## No location here because it's out-of-scope.
-# VARLOC-LABEL: bb.3:
-# VARLOC: DBG_VALUE
+# varloc-label: bb.3:
+# varloc: DBG_VALUE
#
## Common tail for 'test2' -- this is checking that the assignment of undef or
## $noreg in single-assignment mode doesn't lead to trouble further down the
@@ -118,6 +115,7 @@
...
---
name: _Z8bb_to_bb
+debugInstrRef: true
debugValueSubstitutions:
- { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
index e7410a6f977b9..8dddb01f52d3d 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
@@ -57,6 +57,7 @@
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
stack:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
index e76f142b9349d..449ecba16cf49 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
@@ -1,29 +1,17 @@
-# RUN: sed 's_;AAAAAA __' < %s \
-# RUN: | llc -x mir -o - -start-before=phi-node-elimination \
+# RUN: llc %s -o - -start-before=phi-node-elimination \
# RUN: -stop-after=stack-slot-coloring -simplify-mir \
# RUN: -experimental-debug-variable-locations=true \
# RUN: | FileCheck %s --check-prefix=DBGPHIS
-# RUN: sed 's_;BBBBBB __' < %s \
-# RUN: | llc -x mir -o - -start-before=phi-node-elimination \
-# RUN: -stop-after=stack-slot-coloring -simplify-mir \
-# RUN: -experimental-debug-variable-locations=false \
-# RUN: | FileCheck %s --check-prefix=DBGVALS
#
# Test that DBG_PHI instructions do not add "weight" to stack slots and cause
# their coalescing / coloring to change. This is hard to trigger, because it's
# closely coupled with the register allocator. Thus, the test is very
# complicated and hard to reduce.
#
-# In block 13 there are two implementations of variable location tracking, but
-# both are commented out. Use sed in the command lines above to un-comment
-# each one and test what it does: in each case, the PHI should occur in
-# %stack.4 rather than anywhere else.
-#
# Future register allocator changes might change the slot; in that case, just
# update the slot number, so long as it's the same between each RUN.
#
# DBGPHIS: DBG_PHI %stack.4,
-# DBGVALS: DBG_VALUE %stack.4,
--- |
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
@@ -55,6 +43,7 @@
name: amd64_push_arguments
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
@@ -216,11 +205,9 @@ body: |
%2:gr32 = PHI undef %35:gr32, %bb.11, %14, %bb.21
%3:gr64 = PHI %36, %bb.11, %13, %bb.21
- ;AAAAAA %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1
- ;BBBBBB %4:gr32 = PHI %0, %bb.11, %10, %bb.21
+ %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1
%5:gr32 = PHI undef %35:gr32, %bb.11, %9, %bb.21
- ;AAAAAA DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !9
- ;BBBBBB DBG_VALUE %4, 0, !10, !DIExpression(), debug-location !9
+ DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !9
%39:gr8 = COPY %27.sub_8bit
TEST8rr killed %39, %39, implicit-def $eflags, debug-location !9
JCC_1 %bb.18, 5, implicit killed $eflags, debug-location !9
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
index daa4b385815fd..3951929b0eb75 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
@@ -11,6 +11,7 @@
---
name: test
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
debugValueSubstitutions:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
index c4ee8c9df4fed..3e806e43ca9e6 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
@@ -99,6 +99,7 @@
name: bar
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr64 }
- { id: 1, class: gr32 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir b/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
index 6df5dbe8cc322..0b1b9b9957ee9 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
@@ -18,6 +18,7 @@
name: test1
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
index 738c5d4fd762f..238556f7fe00c 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
@@ -109,6 +109,7 @@
name: "\x01?foo@@YAXH at Z"
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
hasWinCFI: true
frameInfo:
stackSize: 8
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
index 9482d13a62819..415b336fc4801 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
@@ -66,6 +66,7 @@
name: soup
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
registers:
- { id: 0, class: gr64 }
- { id: 1, class: gr64 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir
index b20041d04b991..47860f8f47118 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir
@@ -16,6 +16,7 @@
name: test1
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rax' }
# CHECK: debugValueSubstitutions:
@@ -36,6 +37,7 @@ body: |
name: test3
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi' }
# CHECK: debugValueSubstitutions:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir
index d030f7b6b0db6..404ca0c8a42c9 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir
@@ -106,6 +106,7 @@
name: foo
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
frameInfo:
hasCalls: true
fixedStack:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir
index 867dd278de505..f834a9e2ed5f7 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir
@@ -7,6 +7,7 @@ name: test2add_32
# CHECK: name: test2add_32
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$eax' }
- { reg: '$ebp' }
@@ -26,6 +27,7 @@ name: test1mov1add_ebp_32
# CHECK-LABEL: name: test1mov1add_ebp_32
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$eax' }
- { reg: '$ebx' }
@@ -46,6 +48,7 @@ name: testleaadd_ebp_index_32
# CHECK-LABEL: name: testleaadd_ebp_index_32
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$ebx' }
- { reg: '$ebp' }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir
index 48fe95e36c585..75cc3d9480daa 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir
@@ -13,6 +13,7 @@
name: pr43758
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rax' }
- { reg: '$rbp' }
@@ -32,6 +33,7 @@ name: test_mul_spec
# HASWELL-LABEL: name: test_mul_spec
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$edi' }
frameInfo:
@@ -59,6 +61,7 @@ name: testthree
# ATOM-LABEL: name: testthree
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
@@ -84,6 +87,7 @@ name: testfour
alignment: 16
tracksRegLiveness: true
tracksDebugUserValues: true
+debugInstrRef: true
liveins:
- { reg: '$esi' }
frameInfo:
diff --git a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
index 99d0b60265d1f..9bfbec6e9899d 100644
--- a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
+++ b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
@@ -1,10 +1,10 @@
-# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \
-# RUN: -experimental-debug-variable-locations=false \
-# RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCLDV
# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \
# RUN: -experimental-debug-variable-locations=true \
# RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV
#
+# NB: clone of this test for VarLocBasedLDV is in
+# entry-value-of-modified-param2.mir.
+#
#extern void fn1 (int, int, int);
#
#__attribute__((noinline))
@@ -25,9 +25,7 @@
# CHECK: ![[ARG_B:.*]] = !DILocalVariable(name: "b"
# CHECK: ![[ARG_C:.*]] = !DILocalVariable(name: "c"
## TODO: Support KILL instruction, which doesn't clobber parameter value.
-# VARLOCLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression()
# CHECK: DBG_VALUE $edx, $noreg, ![[ARG_C]], !DIExpression(DW_OP_LLVM_entry_value, 1)
-# VARLOCLDV-NOT: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1)
# INSTRREFLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1)
# CHECK-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
#
@@ -93,6 +91,7 @@
---
name: fn2
alignment: 16
+debugInstrRef: true
body: |
bb.0.entry:
liveins: $edi, $esi, $rbx
diff --git a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir
new file mode 100644
index 0000000000000..3ce2758d98f44
--- /dev/null
+++ b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir
@@ -0,0 +1,122 @@
+# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s \
+# RUN: -experimental-debug-variable-locations=false \
+# RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCLDV
+#
+# NB: clone of this file testing InstrRefBasedLDV is in
+# llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
+#
+#extern void fn1 (int, int, int);
+#
+#__attribute__((noinline))
+#int
+#fn2 (int a, int b, int c) {
+# int q = 2 + a;
+#
+# fn1 (5, 6, q);
+#
+# b = b + 7;
+# if (b < 17)
+# return 1;
+# else
+# return 0;
+#}
+#
+# CHECK: ![[ARG_A:.*]] = !DILocalVariable(name: "a"
+# CHECK: ![[ARG_B:.*]] = !DILocalVariable(name: "b"
+# CHECK: ![[ARG_C:.*]] = !DILocalVariable(name: "c"
+## TODO: Support KILL instruction, which doesn't clobber parameter value.
+# VARLOCLDV: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression()
+# CHECK: DBG_VALUE $edx, $noreg, ![[ARG_C]], !DIExpression(DW_OP_LLVM_entry_value, 1)
+# VARLOCLDV-NOT: DBG_VALUE $edi, $noreg, ![[ARG_A]], !DIExpression(DW_OP_LLVM_entry_value, 1)
+# CHECK-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
+#
+--- |
+ ; ModuleID = 'test.c'
+ source_filename = "test.c"
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+ target triple = "x86_64-unknown-linux-gnu"
+
+ ; Function Attrs: noinline nounwind uwtable
+ define dso_local i32 @fn2(i32 %a, i32 %b, i32 %c) local_unnamed_addr !dbg !12 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !20
+ call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression()), !dbg !20
+ call void @llvm.dbg.value(metadata i32 %c, metadata !18, metadata !DIExpression()), !dbg !20
+ %add = add nsw i32 %a, 2, !dbg !21
+ call void @llvm.dbg.value(metadata i32 %add, metadata !19, metadata !DIExpression()), !dbg !20
+ tail call void @fn1(i32 5, i32 6, i32 %add), !dbg !22
+ call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression(DW_OP_plus_uconst, 7, DW_OP_stack_value)), !dbg !20
+ %cmp = icmp slt i32 %b, 10, !dbg !23
+ %. = zext i1 %cmp to i32, !dbg !25
+ ret i32 %., !dbg !26
+ }
+
+ declare !dbg !4 dso_local void @fn1(i32, i32, i32) local_unnamed_addr
+
+ ; Function Attrs: nounwind readnone speculatable willreturn
+ declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+ !llvm.dbg.cu = !{!0}
+ !llvm.module.flags = !{!8, !9, !10}
+ !llvm.ident = !{!11}
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 10.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, nameTableKind: None)
+ !1 = !DIFile(filename: "test.c", directory: "/dir")
+ !2 = !{}
+ !3 = !{!4}
+ !4 = !DISubprogram(name: "fn1", scope: !1, file: !1, line: 1, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
+ !5 = !DISubroutineType(types: !6)
+ !6 = !{null, !7, !7, !7}
+ !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+ !8 = !{i32 2, !"Dwarf Version", i32 4}
+ !9 = !{i32 2, !"Debug Info Version", i32 3}
+ !10 = !{i32 1, !"wchar_size", i32 4}
+ !11 = !{!"clang version 10.0.0"}
+ !12 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 5, type: !13, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !15)
+ !13 = !DISubroutineType(types: !14)
+ !14 = !{!7, !7, !7, !7}
+ !15 = !{!16, !17, !18, !19}
+ !16 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !1, line: 5, type: !7)
+ !17 = !DILocalVariable(name: "b", arg: 2, scope: !12, file: !1, line: 5, type: !7)
+ !18 = !DILocalVariable(name: "c", arg: 3, scope: !12, file: !1, line: 5, type: !7)
+ !19 = !DILocalVariable(name: "q", scope: !12, file: !1, line: 7, type: !7)
+ !20 = !DILocation(line: 0, scope: !12)
+ !21 = !DILocation(line: 7, column: 15, scope: !12)
+ !22 = !DILocation(line: 9, column: 5, scope: !12)
+ !23 = !DILocation(line: 12, column: 11, scope: !24)
+ !24 = distinct !DILexicalBlock(scope: !12, file: !1, line: 12, column: 9)
+ !25 = !DILocation(line: 0, scope: !24)
+ !26 = !DILocation(line: 16, column: 1, scope: !12)
+
+...
+---
+name: fn2
+alignment: 16
+body: |
+ bb.0.entry:
+ liveins: $edi, $esi, $rbx
+
+ DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20
+ DBG_VALUE $esi, $noreg, !17, !DIExpression(), debug-location !20
+ DBG_VALUE $edx, $noreg, !18, !DIExpression(), debug-location !20
+ frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+ CFI_INSTRUCTION def_cfa_offset 16
+ CFI_INSTRUCTION offset $rbx, -16
+ $ebx = MOV32rr $esi
+ DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20
+ renamable $edi = KILL $edi, implicit-def $rdi
+ DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20
+ renamable $edx = LEA64_32r killed renamable $rdi, 1, $noreg, 2, $noreg, debug-location !21
+ DBG_VALUE $edx, $noreg, !19, !DIExpression(), debug-location !20
+ $edi = MOV32ri 5, debug-location !22
+ $esi = MOV32ri 6, debug-location !22
+ CALL64pcrel32 @fn1, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !22
+ DBG_VALUE $ebx, $noreg, !17, !DIExpression(DW_OP_plus_uconst, 7, DW_OP_stack_value), debug-location !20
+ renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !23
+ CMP32ri8 killed renamable $ebx, 10, implicit-def $eflags, debug-location !23
+ renamable $al = SETCCr 12, implicit killed $eflags, implicit killed $eax, implicit-def $eax, debug-location !23
+ $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26
+ CFI_INSTRUCTION def_cfa_offset 8, debug-location !26
+ RET64 $eax, debug-location !26
+
+...
diff --git a/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir b/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
index b980e6abf1b21..35bd7cddca677 100644
--- a/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
+++ b/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
@@ -129,6 +129,7 @@ hasEHScopes: false
hasEHFunclets: false
failsVerification: false
tracksDebugUserValues: true
+debugInstrRef: true
registers: []
liveins:
- { reg: '$ecx', virtual-reg: '' }
diff --git a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
index af7cc754980de..e986bbf141819 100644
--- a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
+++ b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
@@ -1,4 +1,3 @@
-# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=false | FileCheck %s --check-prefixes=CHECK,VARLOCLDV
# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=true | FileCheck %s --check-prefixes=CHECK,INSTRREFLDV
#
# The test case was artificially adjusted, in order to make proper diamond basic
@@ -22,12 +21,10 @@
# CHECK-NEXT: $ebp = MOV32ri 2
# CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
# CHECK: bb.3.if.end
-# VARLOCLDV-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
# INSTRREFLDV: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
#
-## Final two lines: VarLoc LiveDebugValues cannot determine that the DBG_VALUEs
-## down either path of the diamond set the variable to be its original value,
-## wheras instruction referencing LiveDebugValues can.
+## NB: an identical test in llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir
+## checks the same things for VarLocBasedLDV.
#
--- |
; ModuleID = 'test.c'
@@ -114,6 +111,7 @@
---
name: fn2
alignment: 16
+debugInstrRef: true
fixedStack:
- { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
callee-saved-register: '$rbx', callee-saved-restored: true, debug-info-variable: '',
diff --git a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir
new file mode 100644
index 0000000000000..67dcb4394dae1
--- /dev/null
+++ b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir
@@ -0,0 +1,187 @@
+# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s -experimental-debug-variable-locations=false | FileCheck %s --check-prefixes=CHECK,VARLOCLDV
+#
+# The test case was artificially adjusted, in order to make proper diamond basic
+# block structure relevant to the debug entry values clobbering.
+#
+# CHECK: ![[ARG_B:.*]] = !DILocalVariable(name: "b"
+# CHECK: bb.0.entry
+# CHECK: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression()
+# CHECK: bb.1.if.then
+# CHECK: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression()
+# CHECK: $ebx = MOV32rr $esi
+# CHECK-NEXT: DBG_VALUE $ebx, $noreg, ![[ARG_B]], !DIExpression()
+# CHECK-NEXT: $esi = MOV32ri 5
+# CHECK-NEXT: $ebx = MOV32ri 1
+# CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
+# CHECK: bb.2.if.else
+# CHECK: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression()
+# CHECK: $ebp = MOV32rr $esi
+# CHECK: DBG_VALUE $ebp, $noreg, ![[ARG_B]], !DIExpression()
+# CHECK-NEXT: $esi = MOV32ri 1
+# CHECK-NEXT: $ebp = MOV32ri 2
+# CHECK-NEXT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
+# CHECK: bb.3.if.end
+# VARLOCLDV-NOT: DBG_VALUE $esi, $noreg, ![[ARG_B]], !DIExpression(DW_OP_LLVM_entry_value, 1)
+#
+## Final two lines: VarLoc LiveDebugValues cannot determine that the DBG_VALUEs
+## down either path of the diamond set the variable to be its original value,
+## wheras instruction referencing LiveDebugValues can.
+##
+## An identical test in llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
+## checks this for InstrRefBasedLDV.
+#
+--- |
+ ; ModuleID = 'test.c'
+ source_filename = "test.c"
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+ target triple = "x86_64-unknown-linux-gnu"
+
+ ; Function Attrs: noinline nounwind uwtable
+ define dso_local i32 @fn2(i32 %a, i32 %b, i32 %c) local_unnamed_addr !dbg !12 {
+ entry:
+ call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !20
+ call void @llvm.dbg.value(metadata i32 %b, metadata !17, metadata !DIExpression()), !dbg !20
+ call void @llvm.dbg.value(metadata i32 %c, metadata !18, metadata !DIExpression()), !dbg !20
+ %add = add nsw i32 %a, 2, !dbg !21
+ call void @llvm.dbg.value(metadata i32 %add, metadata !19, metadata !DIExpression()), !dbg !20
+ tail call void @fn1(i32 5, i32 6, i32 %add), !dbg !22
+ %cmp = icmp slt i32 %b, 17, !dbg !23
+ br i1 %cmp, label %if.then, label %if.else, !dbg !25
+
+ if.then: ; preds = %entry
+ %add1 = add nsw i32 %b, 7, !dbg !26
+ call void @llvm.dbg.value(metadata i32 %add1, metadata !17, metadata !DIExpression()), !dbg !20
+ tail call void @fn1(i32 5, i32 %add1, i32 %c), !dbg !28
+ br label %if.end, !dbg !29
+
+ if.else: ; preds = %entry
+ %add2 = add nuw nsw i32 %b, 1, !dbg !30
+ call void @llvm.dbg.value(metadata i32 %add2, metadata !17, metadata !DIExpression()), !dbg !20
+ tail call void @fn1(i32 1, i32 %add2, i32 %c), !dbg !32
+ br label %if.end
+
+ if.end: ; preds = %if.else, %if.then
+ %b.addr.0 = phi i32 [ %add1, %if.then ], [ %add2, %if.else ], !dbg !33
+ call void @llvm.dbg.value(metadata i32 %b.addr.0, metadata !17, metadata !DIExpression()), !dbg !20
+ ret i32 %b.addr.0, !dbg !34
+ }
+
+ declare !dbg !4 dso_local void @fn1(i32, i32, i32) local_unnamed_addr
+
+ ; Function Attrs: nounwind readnone speculatable willreturn
+ declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+ !llvm.dbg.cu = !{!0}
+ !llvm.module.flags = !{!8, !9, !10}
+ !llvm.ident = !{!11}
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 10.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, nameTableKind: None)
+ !1 = !DIFile(filename: "test.c", directory: "/dir")
+ !2 = !{}
+ !3 = !{!4}
+ !4 = !DISubprogram(name: "fn1", scope: !1, file: !1, line: 1, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
+ !5 = !DISubroutineType(types: !6)
+ !6 = !{null, !7, !7, !7}
+ !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+ !8 = !{i32 2, !"Dwarf Version", i32 4}
+ !9 = !{i32 2, !"Debug Info Version", i32 3}
+ !10 = !{i32 1, !"wchar_size", i32 4}
+ !11 = !{!"clang version 10.0.0"}
+ !12 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 5, type: !13, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !15)
+ !13 = !DISubroutineType(types: !14)
+ !14 = !{!7, !7, !7, !7}
+ !15 = !{!16, !17, !18, !19}
+ !16 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !1, line: 5, type: !7)
+ !17 = !DILocalVariable(name: "b", arg: 2, scope: !12, file: !1, line: 5, type: !7)
+ !18 = !DILocalVariable(name: "c", arg: 3, scope: !12, file: !1, line: 5, type: !7)
+ !19 = !DILocalVariable(name: "q", scope: !12, file: !1, line: 7, type: !7)
+ !20 = !DILocation(line: 0, scope: !12)
+ !21 = !DILocation(line: 7, column: 15, scope: !12)
+ !22 = !DILocation(line: 9, column: 5, scope: !12)
+ !23 = !DILocation(line: 11, column: 11, scope: !24)
+ !24 = distinct !DILexicalBlock(scope: !12, file: !1, line: 11, column: 9)
+ !25 = !DILocation(line: 11, column: 9, scope: !12)
+ !26 = !DILocation(line: 12, column: 13, scope: !27)
+ !27 = distinct !DILexicalBlock(scope: !24, file: !1, line: 11, column: 17)
+ !28 = !DILocation(line: 13, column: 8, scope: !27)
+ !29 = !DILocation(line: 14, column: 5, scope: !27)
+ !30 = !DILocation(line: 15, column: 13, scope: !31)
+ !31 = distinct !DILexicalBlock(scope: !24, file: !1, line: 14, column: 12)
+ !32 = !DILocation(line: 16, column: 7, scope: !31)
+ !33 = !DILocation(line: 0, scope: !24)
+ !34 = !DILocation(line: 19, column: 5, scope: !12)
+
+...
+---
+name: fn2
+alignment: 16
+fixedStack:
+ - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
+ callee-saved-register: '$rbx', callee-saved-restored: true, debug-info-variable: '',
+ debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
+ callee-saved-register: '$rbp', callee-saved-restored: true, debug-info-variable: '',
+ debug-info-expression: '', debug-info-location: '' }
+body: |
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $edi, $edx, $esi, $rbp, $rbx
+
+ DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20
+ DBG_VALUE $esi, $noreg, !17, !DIExpression(), debug-location !20
+ DBG_VALUE $edx, $noreg, !18, !DIExpression(), debug-location !20
+ frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
+ CFI_INSTRUCTION def_cfa_offset 16
+ frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+ CFI_INSTRUCTION def_cfa_offset 24
+ frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
+ CFI_INSTRUCTION def_cfa_offset 32
+ CFI_INSTRUCTION offset $rbx, -24
+ CFI_INSTRUCTION offset $rbp, -16
+ $ebp = MOV32rr $edx
+ DBG_VALUE $ebp, $noreg, !18, !DIExpression(), debug-location !20
+ renamable $edi = KILL $edi, implicit-def $rdi
+ DBG_VALUE $edi, $noreg, !16, !DIExpression(), debug-location !20
+ renamable $edx = LEA64_32r killed renamable $rdi, 1, $noreg, 2, $noreg, debug-location !21
+ DBG_VALUE $edx, $noreg, !19, !DIExpression(), debug-location !20
+ $edi = MOV32ri 5, debug-location !22
+ CMP32ri8 renamable $ebp, 16, implicit-def $eflags, debug-location !23
+ JCC_1 %bb.2, 15, implicit killed $eflags, debug-location !25
+
+ bb.1.if.then:
+ successors: %bb.3(0x80000000)
+ liveins: $ebp, $ebx, $esi
+
+ $ebx = MOV32rr $esi
+ DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20
+ $esi = MOV32ri 5, debug-location !28
+ $ebx = MOV32ri 1
+ JMP_1 %bb.3
+
+ bb.2.if.else:
+ successors: %bb.3(0x80000000)
+ liveins: $ebp, $ebx, $esi
+
+ $ebp = MOV32rr $esi
+ DBG_VALUE $ebp, $noreg, !17, !DIExpression(), debug-location !20
+ $esi = MOV32ri 1, debug-location !32
+ $ebp = MOV32ri 2
+
+ bb.3.if.end:
+ liveins: $ebx, $edi, $ebp
+
+ $esi = MOV32rr $ebx, debug-location !33
+ $edx = MOV32rr killed $ebp, debug-location !33
+ CALL64pcrel32 @fn1, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !33
+ DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20
+ $eax = MOV32rr killed $ebx, debug-location !34
+ $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34
+ CFI_INSTRUCTION def_cfa_offset 24, debug-location !34
+ $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
+ CFI_INSTRUCTION def_cfa_offset 16, debug-location !34
+ $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
+ CFI_INSTRUCTION def_cfa_offset 8, debug-location !34
+ RET64 killed $eax, debug-location !34
+
+...
+
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir
index 3daeb409ecedd..059f9679cb5bb 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir
@@ -1,4 +1,3 @@
-# RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=false | FileCheck %s --implicit-check-not=DBG_VALUE
# RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=true | FileCheck %s -check-prefix=NEWLDV --implicit-check-not=DBG_VALUE
#
# Test that the DBG_VALUE of ecx below does not get propagated. It is considered
@@ -7,19 +6,8 @@
# loop. There should be no transfer from ecx to ebx -- this is ensured by the
# FileCheck implicit-check-not option.
#
-# FIXME: we successfully prevent the false location (ebx) from being
-# propagated into block 2, but the original transfer isn't yet eliminated.
-# Thus we get no DBG_VALUe in block 2, but an invalid one in block 1.
-#
-# CHECK-LABEL: name: foo
-# CHECK-LABEL: bb.0.entry:
-# CHECK: $ecx = MOV32ri 0
-# CHECK-NEXT: DBG_VALUE
-# CHECK-LABEL: bb.1.loop:
-# CHECK: $ebx = COPY killed $ecx
-# CHECK-NEXT: DBG_VALUE
-#
-# This doesn't occur under value-tracking LiveDebugValues though.
+# An identical test in llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir
+# checks this for VarLocBasedLDV.
#
# NEWLDV-LABEL: name: foo
# NEWLDV-LABEL: bb.0.entry:
@@ -61,6 +49,7 @@
name: foo
alignment: 4
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$edi' }
frameInfo:
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir
new file mode 100644
index 0000000000000..80e9926b4a276
--- /dev/null
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer2.mir
@@ -0,0 +1,106 @@
+# RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -run-pass=livedebugvalues -experimental-debug-variable-locations=false | FileCheck %s --implicit-check-not=DBG_VALUE
+#
+# Test that the DBG_VALUE of ecx below does not get propagated. It is considered
+# live-in on LiveDebugValues' first pass through the loop, but on the second it
+# should be removed from the InLocs set because it gets clobbered inside the
+# loop. There should be no transfer from ecx to ebx -- this is ensured by the
+# FileCheck implicit-check-not option.
+#
+# FIXME: we successfully prevent the false location (ebx) from being
+# propagated into block 2, but the original transfer isn't yet eliminated.
+# Thus we get no DBG_VALUe in block 2, but an invalid one in block 1.
+#
+# CHECK-LABEL: name: foo
+# CHECK-LABEL: bb.0.entry:
+# CHECK: $ecx = MOV32ri 0
+# CHECK-NEXT: DBG_VALUE
+# CHECK-LABEL: bb.1.loop:
+# CHECK: $ebx = COPY killed $ecx
+# CHECK-NEXT: DBG_VALUE
+#
+# An identical test in llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir
+# checks this for InstrRefBasedLDV.
+
+--- |
+ source_filename = "live-debug-values-remove-range.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+ define i32 @foo(i32 %bar) !dbg !4 {
+ entry:
+ br label %loop
+ loop:
+ br label %loop
+ exit:
+ ret i32 %bar
+ }
+
+ !llvm.module.flags = !{!0, !1}
+ !llvm.dbg.cu = !{!2}
+
+ !0 = !{i32 2, !"Debug Info Version", i32 3}
+ !1 = !{i32 2, !"Dwarf Version", i32 4}
+ !2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "beards", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+ !3 = !DIFile(filename: "bees.cpp", directory: ".")
+ !4 = distinct !DISubprogram(name: "nope", scope: !3, file: !3, line: 1, type: !5, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !8)
+ !5 = !DISubroutineType(types: !6)
+ !6 = !{!7}
+ !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+ !8 = !{!9}
+ !9 = !DILocalVariable(name: "thin", scope: !4, file: !3, line: 1, type: !7)
+ !10 = !DILocation(line: 1, scope: !4)
+
+...
+---
+name: foo
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$edi' }
+frameInfo:
+ stackSize: 8
+ offsetAdjustment: -8
+ maxAlignment: 1
+ adjustsStack: true
+ hasCalls: true
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 8
+fixedStack:
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$rbx' }
+machineFunctionInfo: {}
+body: |
+ bb.0.entry:
+ liveins: $edi, $rbx
+
+ frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+ CFI_INSTRUCTION def_cfa_offset 16
+ CFI_INSTRUCTION offset $rbx, -16
+ $ebx = MOV32rr $edi
+ $eax = MOV32ri 0, debug-location !10
+ $ecx = MOV32ri 0, debug-location !10
+ DBG_VALUE $ecx, $noreg, !9, !DIExpression(), debug-location !10
+ $edi = MOV32ri 0, debug-location !10
+ $esi = MOV32ri 0, debug-location !10
+
+ bb.1.loop:
+ successors: %bb.1, %bb.2
+ liveins: $ebx, $eax, $ecx, $edi, $esi
+
+ $eax = COPY $ecx, debug-location !10
+ $ebx = COPY killed $ecx, debug-location !10
+ $ecx = COPY killed $edi, debug-location !10
+ $edi = COPY killed $esi, debug-location !10
+ $esi = MOV32ri 1, debug-location !10
+ TEST8ri killed renamable $al, 1, implicit-def $eflags
+ JCC_1 %bb.1, 5, implicit killed $eflags, debug-location !10
+
+ bb.2.exit:
+ liveins: $ebx
+
+ $eax = MOV32rr killed $ebx, debug-location !10
+ $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
+ CFI_INSTRUCTION def_cfa_offset 8
+ RET64 $eax, debug-location !10
+
+...
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir
index 1d6bf70859992..78935e1107474 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir
@@ -202,6 +202,7 @@
---
name: foo
tracksRegLiveness: true
+debugInstrRef: true
registers: []
liveins:
- { reg: '$rdi', virtual-reg: '' }
@@ -245,6 +246,7 @@ body: |
---
name: bar
tracksRegLiveness: true
+debugInstrRef: true
registers: []
liveins:
- { reg: '$rdi', virtual-reg: '' }
@@ -290,6 +292,7 @@ body: |
---
name: baz
tracksRegLiveness: true
+debugInstrRef: true
registers: []
liveins:
- { reg: '$rdi', virtual-reg: '' }
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
index e5d751d994aa8..d093685dc15db 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
@@ -111,6 +111,7 @@ legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
+debugInstrRef: true
registers:
liveins:
- { reg: '$edi', virtual-reg: '' }
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
index 9ecf9c16772f5..881d391fee812 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
@@ -265,6 +265,7 @@ regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
+debugInstrRef: true
hasWinCFI: false
registers: []
liveins:
@@ -385,6 +386,7 @@ body: |
name: g
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
frameInfo:
@@ -462,6 +464,7 @@ body: |
name: h
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
frameInfo:
@@ -576,6 +579,7 @@ body: |
name: i
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
frameInfo:
@@ -690,6 +694,7 @@ body: |
name: j
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
frameInfo:
@@ -800,6 +805,7 @@ body: |
name: k
alignment: 16
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
- { reg: '$r10', virtual-reg: '' }
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir
index 91892102fc5ee..763411aabea44 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir
@@ -105,6 +105,7 @@
---
name: f
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
- { reg: '$rsi', virtual-reg: '' }
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
index 95d2c879f09b6..aca28e2bceb18 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
@@ -69,6 +69,7 @@
---
name: _Z8bb_to_bb
tracksRegLiveness: true
+debugInstrRef: true
liveins:
- { reg: '$rdi', virtual-reg: '' }
stack:
diff --git a/llvm/test/DebugInfo/X86/instr-ref-flag.ll b/llvm/test/DebugInfo/X86/instr-ref-flag.ll
index f9d5f99edf77f..34f22a728e2d0 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-flag.ll
+++ b/llvm/test/DebugInfo/X86/instr-ref-flag.ll
@@ -13,7 +13,9 @@
;; by llc by default, and that it can be turned explicitly on or off as
;; desired.
+; INSTRREFON: debugInstrRef: true
; INSTRREFON: DBG_INSTR_REF
+; INSTRREFOFF: debugInstrRef: false
; INSTRREFOFF: DBG_VALUE
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir b/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir
index 8496f17b0f02f..7ac5923464105 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir
+++ b/llvm/test/DebugInfo/X86/instr-ref-track-clobbers.mir
@@ -90,6 +90,7 @@ hasEHScopes: false
hasEHFunclets: false
failsVerification: false
tracksDebugUserValues: true
+debugInstrRef: true
registers: []
liveins:
- { reg: '$rdi', virtual-reg: '' }
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