[PATCH] D141895: [AMDGPU] Add missing physical register check in SIFoldOperands::tryFoldLoad

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir:26-34
+    %3:vgpr_32 = COPY $vgpr3
+    %2:vgpr_32 = COPY $vgpr2
+    %1:vgpr_32 = COPY $vgpr1
+    %0:vgpr_32 = COPY $vgpr0
+    %12:vreg_64_align2 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
+    %6:sreg_32 = S_MOV_B32 2
+    %7:vreg_64_align2 = V_LSHLREV_B64_e64 killed %6, %12, implicit $exec
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If you use -run-pass=none, it will clean up and compact these register numbers for you


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141895/new/

https://reviews.llvm.org/D141895