[PATCH] D142166: [X86] In `shouldExpandLogicAtomicRMWInIR` return `CmpXChg` instead of asserting if we don't match op(0)

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n created this revision.
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The old code from `D140939` asserted that the AtomicRMW was operand(0)
which isn't necessarily the case.

It was previously relatively safe to assume this, as we only matched
constants (which cannonicalize to op(1) being constant), but now we
can match non-constant power of 2 which don't have that
canonicalization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142166

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -31529,7 +31529,9 @@
       AI->getParent() != I->getParent())
     return AtomicExpansionKind::CmpXChg;
 
-  assert(I->getOperand(0) == AI);
+  if (I->getOperand(0) != AI)
+    return AtomicExpansionKind::CmpXChg;
+
   // The following instruction must be a AND single bit.
   if (BitChange.second == ConstantBit || BitChange.second == NotConstantBit) {
     auto *C1 = dyn_cast<ConstantInt>(AI->getValOperand());


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