[PATCH] D139827: [RISCV][Asan] Use dynamic shadow offset to make it work on different width of virtual-memory system.

Shabnam via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 19 11:52:19 PST 2023


shabnam4b added a comment.

In D139827#4042468 <https://reviews.llvm.org/D139827#4042468>, @kito-cheng wrote:

>> Supporting too many address space bits can introduce significant hidden maintenance burden and performance implication, e.g. using SizeClassAllocator32 for LeakSanitizer (standalone or asan/hwasan integrated) is extremely slow.
>> See D137666 <https://reviews.llvm.org/D137666> that AArch64 msan dropped <48-bit VMA. A line needs to be drawn.
>
> As I know there is still many RISC-V core are implement with Sv39 for now, we might able to drop support in future but it's not good timing for now I think.
>
> ---
>
> Will defer few more days to commit for continue the discussion.

Ok, thanks for checking! Could you please merge this PR if there is no issue left?


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