[PATCH] D142144: [RISCV][Driver] Add -rvv-vector-bits= option similar to -sve-vector-bits=

[Craig Topper via Phabricator via llvm-commits]

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This option will control the vscale min/max.

I have left out the '+' support that SVE supports for now. We already
have minimum controlled by the Zvl*b extension so this didn't seem that
useful.

In addition to 64, 128, 256, 512, ..., 65536, I have added an extra
value "zvl" that will use the value from Zvl*b as the min and max.
This avoids repeating the numeric value in two places or to get
min/max from -mcpu.

The primary effect of this option today is simplification of stack
address calculations for RVV vectors and avoiding the use of
vrgatherei16 in some cases if we know there are less than 256 elements.

Future patches may add something similar to the arm_sve_vector_bits
attribute to allow RVV vectors to be used in structs and global
variables.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142144

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-rvv-vector-bits.c

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