[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.
Herald added a subscriber: luke.


================
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:765
 
+  if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvknha") || Exts.count("zvkns") ||
+       Exts.count("zvksed") || Exts.count("zvksh")) && !HasVector)
----------------
Line exceeds 80 characters


================
Comment at: llvm/lib/Target/RISCV/RISCV.td:473
+def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
+                                AssemblerPredicate<(all_of FeatureStdExtZvkb),
+                                "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
----------------
Indented too much


================
Comment at: llvm/lib/Target/RISCV/RISCV.td:480
+def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
+                                AssemblerPredicate<(all_of FeatureStdExtZvkg),
+                                "'Zvkg' (Vector GCM instructions for Cryptography.)">;
----------------
Indented too much


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672