[PATCH] D142122: [SVE][InstrFormats] Explcitly set hasSideEffects for all SVE instructions.

[Paul Walker via Phabricator via llvm-commits]

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The instruction property hasSideEffects relies on the presence of
tablegen isel patterns when constructing its value, unless
specifically overriden. Since adding SVE scheduling information
we've noticed this property flip-flop as isel patterns have been
updated. To make things consistent (and correct) this patch
explicitly sets the property for all SVE instructions.

This has resulted in the following notable changes:

- Normal load and store instructions no longer report having side effects.
- All prefetch instructions correctly report having side effects.
- FFR related instructions continue to report having side effects. This is likely overkill but I've chosen to remain cautious here.
- Most all integer instructions no longer report having side effects.
- Most all floating point instructions no longer report having side effects, but do now report their potential for raising FP exceptions. I do not know how to test the latter so I've again took a caution route of taging all floating point instructions except for DUPs.
- The conflict detection intrinsics now report they don't touch memory.

NOTE: SVE isel makes significant use of psuedo instructions but
this patch makes no effort to update them.



NOTE: We'll need a similar patch for SME but without a scheduling
model it'll be harder to verify the results.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142122

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
  llvm/test/CodeGen/AArch64/sve-insert-vector.ll
  llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

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