[PATCH] D141895: [AMDGPU] Add missing physical register check in SIFoldOperands::tryFoldLoad

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/swdev373493.ll:4
+
+ at a0000000000000000000000000000000004040 = external protected addrspace(4) externally_initialized global [4096 x i64], align 16
+
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opt -passes=metarenamer?


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Comment at: llvm/test/CodeGen/AMDGPU/swdev373493.mir:2
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs | FileCheck %s
+--- |
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This can be reduced, you can try llvm-reduce mir handling


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141895/new/

https://reviews.llvm.org/D141895