[PATCH] D141946: [AArch64][SME2] Add multi-vector fused multiply-add/subtract intrinsics

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll:44
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+; Test to ensure the correct register class is used (first register in the list should be a multiple of 2)
+define void @multi_vector_add_single_vg1x2_s_regclass(i32 %slice, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zm) {
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CarolineConcatto wrote:
> Which instructions should have the first register multiple of two?
> Is the fmla? If so the first register in the list is z3.s, no? If so, is this comment correct?
You're right, this comment is incorrect. The first register in the list for the 'multiple and single vector' fmla instructions don't need to be multiples of 2 or 4, so I don't think this test is useful.
I've removed this and the `@multi_vector_add_single_vg1x4_d_regclass` test below and replaced them with similar tests for the multi & indexed instructions instead.


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  https://reviews.llvm.org/D141946/new/

https://reviews.llvm.org/D141946