[llvm] 97cb619 - [RISCV] Use canonical move instruction in RISCVAsmPrinter::EmitHwasanMemaccessSymbols.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-01-18T11:38:39-08:00
New Revision: 97cb6191173ea4de67e7c5a2f0dbfe61109a5c71

URL: https://github.com/llvm/llvm-project/commit/97cb6191173ea4de67e7c5a2f0dbfe61109a5c71
DIFF: https://github.com/llvm/llvm-project/commit/97cb6191173ea4de67e7c5a2f0dbfe61109a5c71.diff

LOG: [RISCV] Use canonical move instruction in RISCVAsmPrinter::EmitHwasanMemaccessSymbols.

We were using an OR with X0 which is the canonical move for AArch64.
The canonical move for RISC-V is ADDI reg1, reg2, 0.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D142044

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index f1af99ac8b59..a4b999e6aa3b 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -449,10 +449,10 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
                                                                             8),
         MCSTI);
     if (Reg != RISCV::X10)
-      OutStreamer->emitInstruction(MCInstBuilder(RISCV::OR)
+      OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
                                        .addReg(RISCV::X10)
-                                       .addReg(RISCV::X0)
-                                       .addReg(Reg),
+                                       .addReg(Reg)
+                                       .addImm(0),
                                    MCSTI);
     OutStreamer->emitInstruction(
         MCInstBuilder(RISCV::ADDI)