[PATCH] D142044: [RISCV] Use canonical move instruction in RISCVAsmPrinter::EmitHwasanMemaccessSymbols.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 18 10:40:24 PST 2023


craig.topper created this revision.
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We were using an OR with X0 which is the canonical move for AArch64.
The canonical move for RISC-V is ADDI reg1, reg2, 0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142044

Files:
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp


Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -443,10 +443,10 @@
                                                                             8),
         MCSTI);
     if (Reg != RISCV::X10)
-      OutStreamer->emitInstruction(MCInstBuilder(RISCV::OR)
+      OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
                                        .addReg(RISCV::X10)
-                                       .addReg(RISCV::X0)
-                                       .addReg(Reg),
+                                       .addReg(Reg)
+                                       .addImm(0),
                                    MCSTI);
     OutStreamer->emitInstruction(
         MCInstBuilder(RISCV::ADDI)


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