[PATCH] D141464: [X86]: Match (xor TSize - 1, ctlz) to `bsr` instead of `lzcnt` + `xor`

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:52108
+  auto *C = dyn_cast<ConstantSDNode>(OpSizeTM1);
+  if (C == nullptr)
+    return SDValue();
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RKSimon wrote:
> if (!C)
> if (!C)

Are the two equivilent? Always thought `!C` is a zero/non-zero check but `nullptr != 0` is techincally possible.


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Comment at: llvm/test/CodeGen/X86/clz.ll:968
 ; the most significant bit, which is what 'bsr' does natively.
 ; FIXME: We should probably select BSR instead of LZCNT in these circumstances.
 define i32 @ctlz_bsr(i32 %n) {
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RKSimon wrote:
> pengfei wrote:
> > The FIXME is solved :)
> > But maybe better to leave a comment the `FASTLZCNT` is intended.
> What target can manage 1c latency bsr?
> What target can manage 1c latency bsr?

Zen4 and I think a few other AMD ones (although more have 1c lzcnt and expensive bsr).


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https://reviews.llvm.org/D141464