[PATCH] D142032: [AArch64][SME2] Add multi-vector convert to/from floating-point intrinsic

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
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Add the following intrinsic:

  FCVT
  BFCVT
  FCVTZS
  FCVTZU
  SCVTF
  UCVTF

This patch also adds SelectCVTIntrinsic to handle the cases when the
intrinsic returns multiple (two or four) outputs

NOTE: These intrinsics are still in development and are subject to future changes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142032

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/CodeGen/AArch64/sme2-intrinsics-cvt.ll

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