[PATCH] D141946: [AArch64][SME2] Add multi-vector fused multiply-add/subtract intrinsics

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added a comment.

Hi Kerry,
I had a look and it looks all ok.
I just have a couple of questions if you don't mind.
Carol



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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2217
   def NAME : sme2_multi_vec_array_vg2_index<0b1, {op{3},?,?,op{2-0}}, MatrixOp32, multi_vector_ty, vector_ty,
-                                             VectorIndexS,  mnemonic> {
+                                             VectorIndexS,  mnemonic>, SMEPseudo2Instr<NAME, 1> {
     bits<2> i;
----------------
Should we replace that as well:
s/VectorIndexS/VectorIndexS32b/


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2228
         (!cast<Instruction>(NAME) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
         multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexS:$i), 0>;
 }
----------------
And here too:
s/VectorIndexS/VectorIndexS32b/
I am not sure, if this should be replaces, but if so. We should have a look in the other classes here.


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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll:44
+
+; Test to ensure the correct register class is used (first register in the list should be a multiple of 2)
+define void @multi_vector_add_single_vg1x2_s_regclass(i32 %slice, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zm) {
----------------
Which instructions should have the first register multiple of two?
Is the fmla? If so the first register in the list is z3.s, no? If so, is this comment correct?


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