[PATCH] D141937: [SVE] Add intrinsics for integer binops that explicitly undefine the result for inactive lanes.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

For the original ACLE design I made a mistake by assuming representing all the builtins via merging intrinsics would not affect code quality. So my rational here is not to make the same mistake again and thus at least at the point of IR creation have the IR capture the maximum amount of information. For a more practical reason, please consider:

  add_u(pg, A, lsr_m(pg,B,C) => usra(A,B,C)	(Valid)
  add(A, lsr_m(pg,B,C) => usra(A,B,C)		(Invalid)

Also, for what it's worth the lowering of add intrinsics to ISD::ADD came at a time when maximising code quality during isel was not possible.  I believe D141938 <https://reviews.llvm.org/D141938> changes that so we may end up reverting some of those transforms. It'll just depends on what common combines we might loose out on. Although, there is an argument that those combines should be replicated for the predicated nodes anyway.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141937/new/

https://reviews.llvm.org/D141937