[PATCH] D141834: [RISCV][NFC] Use uncompressInst to relax instructions
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 17 21:57:35 PST 2023
pcwang-thead updated this revision to Diff 490035.
pcwang-thead added a comment.
Rebase.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D141834/new/
https://reviews.llvm.org/D141834
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -167,36 +167,17 @@
void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
const MCSubtargetInfo &STI) const {
- // TODO: replace this with call to auto generated uncompressinstr() function.
MCInst Res;
switch (Inst.getOpcode()) {
default:
llvm_unreachable("Opcode not expected!");
case RISCV::C_BEQZ:
- // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
- Res.setOpcode(RISCV::BEQ);
- Res.addOperand(Inst.getOperand(0));
- Res.addOperand(MCOperand::createReg(RISCV::X0));
- Res.addOperand(Inst.getOperand(1));
- break;
case RISCV::C_BNEZ:
- // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
- Res.setOpcode(RISCV::BNE);
- Res.addOperand(Inst.getOperand(0));
- Res.addOperand(MCOperand::createReg(RISCV::X0));
- Res.addOperand(Inst.getOperand(1));
- break;
case RISCV::C_J:
- // c.j $imm -> jal X0, $imm.
- Res.setOpcode(RISCV::JAL);
- Res.addOperand(MCOperand::createReg(RISCV::X0));
- Res.addOperand(Inst.getOperand(0));
- break;
case RISCV::C_JAL:
- // c.jal $imm -> jal X1, $imm.
- Res.setOpcode(RISCV::JAL);
- Res.addOperand(MCOperand::createReg(RISCV::X1));
- Res.addOperand(Inst.getOperand(0));
+ bool Success = RISCVRVC::uncompress(Res, Inst, STI);
+ assert(Success && "Can't uncompress instruction");
+ (void)Success;
break;
}
Inst = std::move(Res);
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