[PATCH] D141748: [WoA] Use fences for sequentially consistent stores/writes

[Billy Robert O'Neal III via Phabricator via llvm-commits]

BillyONeal added a comment.

In D141748#4060636 <https://reviews.llvm.org/D141748#4060636>, @efriedma wrote:

> The explanation makes sense.
>
> Can we make this specifically apply to _Interlocked* functions, instead of all atomics on Windows targets?  I'd prefer not to impose this performance penalty on other users of atomics if we can avoid it.

To be clear this is about the ABI of std::atomic, and we are likely to change that when we get to break that Someday. Interlocked doesn't come with plain load/store ops (because, I assume, it was assumed plain volatiles were sufficient for that)

> It looks like for atomic rmw ops, MSVC generates one barrier, not two; can we do the same?

Let me poke our backend folks...


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