[PATCH] D141980: [X86] Transform slow LEA_B_I_D/LEA_SLOWBASE_I -> LEA_IS_D/LEA_IS iff base == index

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added a comment.

In D141980#4060945 <https://reviews.llvm.org/D141980#4060945>, @pengfei wrote:

> scale > 1 also has bad performation on some microarch, see Intel SOM.

Any idea which micro arch? I don't see any and can't see any reference in SOM.
SOM says:

  For LEA instructions with three source operands and some specific situations, instruction latency has
  increased to 3 cycles, and must dispatch via port 1:
  — LEA that has all three source operands: base, index, and offset.
  — LEA that uses base and index registers where the base is EBP, RBP, or R13.
  — LEA that uses RIP relative addressing mode.
  — LEA that uses 16-bit addressing mode.

But if that is the case below in l902-l910 we have:

  // lea offset(%base,%index,scale), %dst =>
  // lea offset( ,%index,scale), %dst; add %base,%dst
  NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
              .add(Dest)
              .addReg(0)
              .add(Scale)
              .add(Index)
              .add(Offset)
              .add(Segment);

Shouldn't that be removed then?


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https://reviews.llvm.org/D141980